[v2,3/5] clk: qcom: gcc-ipq6018: remove alpha values from NSS Crypto PLL's config

Commit Message

Gabor Juhos Oct. 28, 2024, 6:48 p.m. UTC

Since both the 'alpha' and 'alpha_hi' members of the configuration is
initialized with zero values, the output rate of the PLL will be the
same whether alpha mode is enabled or not.

Remove the initialization of the alpha* members to make it clear that
alpha mode is not required to get the desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the clk_alpha_pll_set_rate()
function will get reset the ALPHA_EN bit when the PLL's rate changes,
so dropping 'alpha_en_mask' is safe.

While at it, also add a comment to indicate the frequency the PLL runs
at with the current configuration.

No functional changes, the PLL runs at 1.2 GHz both before and after
the change.

Tested on Xiaomi Mi Router AX1800 (IPQ6018, out-of-tree board).

Reviewed-by: Dmitry Baryshkov <[e-mail]>
Signed-off-by: Gabor Juhos <[e-mail]>
---
Changes in v2:
  - extend the commit message to indicate that dropping 'alpha_en_mask' is safe
  - add RB tag from Dmitry
  - Link to v1: https://lore.kernel.org/r/[e-mail]
---
 drivers/clk/qcom/gcc-ipq6018.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Patch

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index ab0f7fc665a9790dd8edba0cf4b86c5c672a337d..d861191b0c85ccc105ac0e62d7a68210c621fc13 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4194,10 +4194,9 @@  static const struct alpha_pll_config ubi32_pll_config = {
 	.test_ctl_hi_val = 0x4000,
 };
 
+/* 1200 MHz configuration */
 static const struct alpha_pll_config nss_crypto_pll_config = {
 	.l = 0x32,
-	.alpha = 0x0,
-	.alpha_hi = 0x0,
 	.config_ctl_val = 0x4001055b,
 	.main_output_mask = BIT(0),
 	.pre_div_val = 0x0,
@@ -4206,7 +4205,6 @@  static const struct alpha_pll_config nss_crypto_pll_config = {
 	.post_div_mask = GENMASK(11, 8),
 	.vco_mask = GENMASK(21, 20),
 	.vco_val = 0x0,
-	.alpha_en_mask = BIT(24),
 };
 
 static struct clk_hw *gcc_ipq6018_hws[] = {