From patchwork Mon Oct 28 14:04:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13853502 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 969641DDC21; Mon, 28 Oct 2024 14:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124295; cv=none; b=QnTKxsRNXlDV3jyUxNv5ZkSu6GnTQec5tjzdlf7QF2Rt+Q4yPGOQKXJ/y8FzGXA6qyR7EDWQmwrxesBxwMyuuHRESbXLOmEvoe+r5YI3PRo9vfF3kcilZbaBnZWA/rJuPmwtP6srbo2OP2YgHUdSAMZqClT7BrdDndWhmzM3ZGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124295; c=relaxed/simple; bh=vG3DMDeDtIAizT7d5yDcrA3ylY/kTZ9djArHmSaKkT0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XLHUoyqHglT4N9LduJUrAj9WEOFVdOR3J0yMt+EfwosRPBQUNGmt5QrKtQ2ZcIV9daWsqAPkY/79jBpCNNgQugFNuWEwuK5w+PornMEMy2U4ff50fpLrYDsHzzxDg/TeMahhhuhSsI3r67mI0k3rRGzkSmyj3XN67Kt+zkA9Xak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=dVniO1bY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="dVniO1bY" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SAobE5025943; Mon, 28 Oct 2024 14:04:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= a2RwsBlyYk5yXPCHBOPKoRRajFMjsEiv0ypIDwekaw4=; b=dVniO1bYOfidIURN eEI3Ia4lf9SdP9XxaVt3QG5xmS0T5eFxhTtS8aLJw8NtXVIne0LmZru4aoSRMn43 PHIZUMiYyz+44AcZ9OnWNh1Mrh73g098f8Nv46PAAWoivOBLzpdNTCSRX4O2Pymh Wrd9KbA1bqvmU5kFj2P7f4iJhpycZxJQUKqV6MVv7TfnZCffiQVNGzJ6mrWQHKDz HON+n0C/LYIfBq5SWFuAflsJbRkNvkL3WBR7XFQsSnqDi6TJvggtDMZCFUOvARWo sHF60TVulRbTGkjo52XpqS3sUU5PuQy/QdldB3USt2EJKKyHCUmXZGjd3ldRGcX4 Bl653Q== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gs6e56dx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 14:04:39 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SE4d1D031095 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 14:04:39 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 07:04:33 -0700 From: Luo Jie Date: Mon, 28 Oct 2024 22:04:10 +0800 Subject: [PATCH v5 3/4] arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controller Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241028-qcom_ipq_cmnpll-v5-3-339994b0388d@quicinc.com> References: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> In-Reply-To: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie , Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730124258; l=1117; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=vG3DMDeDtIAizT7d5yDcrA3ylY/kTZ9djArHmSaKkT0=; b=hTGPQesl++00FNlvMJP2FNy6ROsMQiE63w9cf5F77NZlLxqosGsHZDRDkEgRJUaZ1bSWc/QWB 6zHoecMFhXaDZqyRJ/vaUYl2DTL/6/qErQyH6TLl95BBvnYVEH4Uhsc X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Db1p4D7wvNtk9cOkThZAX1QmFbCjUxvf X-Proofpoint-GUID: Db1p4D7wvNtk9cOkThZAX1QmFbCjUxvf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=784 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280113 The CMN PLL hardware block is available in the Qualcomm IPQ SoC such as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. This CMN PLL hardware block does not provide any other specific function on the IPQ SoC other than enabling output clocks to Ethernet related devices. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luo Jie --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..11aefa9ef7b8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1308,6 +1308,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y