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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2528; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=L856afxfFYTrzTjleMcDff0M5LSJvcUyglLdt4As0hg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFaONQvWVA4bP4yQAg2u1VE2uFOJH4JqIlyKjuL E+b5cDeJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWgAKCRB33NvayMhJ0QTMD/ 9Ym4y6wn5ANBhacJSlVGVq+pieT1LNiuwmZiuqSYT3/FAUZxjXIcuGnBVPWROkU8WG/7Ea0BV6zx7G GaAg7kVOc6fwaAXUEgidaO+BO0d/C6XjOF75YoaVwNzEQ632acKIeBWDCPnPKv58KD+Nqw/LQTpl+2 Pl+4ZitIKwP5OlbelgcghCk+KiNxKPRxpiOi4OXJeJPLGh2eAKQCWQae7uSKmHofFvSefqK3+3DIlJ HBQpyNslSFCzh5BZ/CPPCBfyc+rNP7TYAxZHT3EbolVv2Ti8Q2PuAcFJcKHVjZKAsQU5TB/y1Hikhx 3900PeUp1zuXz+LiCiACvsOKvnDAQAEsHUtMwEj6rSyUdixVbGCZHOsCpCMxtfeVyxm/A7b7R96CNN xCIkhzd//K64UKDkLx/oARBg/KC5TWNblhqNWee2XVrc2civdB1OWbFWSk2mt6J8S2/TL6h17/Vb9v vJl1D4wrMkfcsQ+48D6qY8vzG4BYACQGe3qw7xXqmgaj24pHeBPGfRMTI5/3obZsMIzHSAWzenpqDT EccOZwyzZtuPN2FJzDiPPdkiqoQV82UdKrsyKgNjS6l9NYraZ+Pwc/G9njaCkRkMW8OSHPGulWOj3O 8QmSiYESfdbe44ubCXHV1PNcAlfkTHDA1s/n1O9Q4+qzWx0rV5ujJhUziC8Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Now all the DDR bandwidth voting via the GPU Management Unit (GMU) is in place, declare the Bus Control Modules (BCMs) and the corresponding parameters in the GPU info struct and add the GMU_BW_VOTE feature bit to enable it. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3..7cb96d524f76df67c6ee4377827a38384c1b343a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1379,7 +1379,8 @@ static const struct adreno_info a7xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | - ADRENO_FEAT_PREEMPTION, + ADRENO_FEAT_PREEMPTION | + ADRENO_FEAT_GMU_BW_VOTE, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1388,6 +1389,16 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202, + .bcm = { + [0] = { .name = "SH0", .buswidth = 16 }, + [1] = { .name = "MC0", .buswidth = 4 }, + [2] = { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 4192 * SZ_1K, @@ -1424,7 +1435,8 @@ static const struct adreno_info a7xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | - ADRENO_FEAT_PREEMPTION, + ADRENO_FEAT_PREEMPTION | + ADRENO_FEAT_GMU_BW_VOTE, .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1432,6 +1444,16 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202, + .bcm = { + [0] = { .name = "SH0", .buswidth = 16 }, + [1] = { .name = "MC0", .buswidth = 4 }, + [2] = { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 3572 * SZ_1K,