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Fri, 22 Nov 2024 21:45:04 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 23 Nov 2024 07:44:55 +0200 Subject: [PATCH v2 2/3] drm/msm/mdss: reuse defined bitfields for UBWC 2.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241123-msm-mdss-ubwc-v2-2-41344bc6ef9c@linaro.org> References: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> In-Reply-To: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Connor Abbott , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2725; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=RCQrEDg9Jf371ZVvZyxUNDcRd0dYuvhxst+HGMFH54g=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnQWvaJC/hfMr53Xnp+aU8MlaVVv17sAyaPbzhy 7IVBxOCTZ2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0Fr2gAKCRCLPIo+Aiko 1dkOB/401lf+nszpksFsYEwE+4wZaylb0UuOyr6FiEosWoZPPznYOblrU4AVUIRMXw3X+cqS+cK jLxPa+zbtH+nUwqueapeeZHBZ6cjSuvYAvDUU77o/kz4/4gfdjyLSMvS2jJCRNFbvINciLFo78z soguSxPjKZ5eS+o4seBUMs6iuEGAstV1VGVfOI/tsTRWyCb6Wg1UxOpE8mIAgVz7SZhQOBtNjvQ VXCcQcK8JzupqDL9bJyAGAfGjKitrHrnzPpD2vopgG/x/WhsdtIGKevxK4aYoG5OhhG57xIe2ox AQWwwp26Gx5Tgj7y6lAtqfaiTCZLz5umIPQqiamiivqCkqLa X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow other msm_mdss_setup_ubwc_dec_nn functions and use individual bits instead of just specifying the value to be programmed to the UBWC_STATIC register. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- drivers/gpu/drm/msm/msm_mdss.h | 1 - 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 4b57f39bec4e6232a0f5b4d49f8ae1200e74ac78..2fdad0fa4bc159e9a10755da2c0402fd87734aee 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -166,8 +166,16 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data = msm_mdss->mdss_data; + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); - writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + if (data->ubwc_bank_spread) + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->ubwc_enc_version == UBWC_1_0) + value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) @@ -587,7 +595,8 @@ static const struct msm_mdss_data sa8775p_data = { static const struct msm_mdss_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, - .ubwc_static = 0x1e, + .ubwc_swizzle = 6, + .ubwc_bank_spread = true, .highest_bank_bit = 0x1, .reg_bus_bw = 76800, }; @@ -638,7 +647,7 @@ static const struct msm_mdss_data sm6350_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = 6, - .ubwc_static = 0x1e, + .ubwc_bank_spread = true, .highest_bank_bit = 1, .reg_bus_bw = 76800, }; @@ -661,7 +670,7 @@ static const struct msm_mdss_data sm6115_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = 7, - .ubwc_static = 0x11f, + .ubwc_bank_spread = true, .highest_bank_bit = 0x1, .reg_bus_bw = 76800, }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 715e1426093de5a4f3b7d2b66b889573c30b7b5c..14dc53704314558841ee1fe08d93309fd2233812 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -11,7 +11,6 @@ struct msm_mdss_data { /* can be read from register 0x58 */ u32 ubwc_dec_version; u32 ubwc_swizzle; - u32 ubwc_static; u32 highest_bank_bit; bool ubwc_bank_spread; bool macrotile_mode;