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Wed, 27 Nov 2024 10:47:55 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 27 Nov 2024 02:47:51 -0800 From: Yongxing Mou Date: Wed, 27 Nov 2024 18:45:14 +0800 Subject: [PATCH 2/2] arm64: dts: qcom: qcs8300-ride: Enable Display Port Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241127-dp_dts_qcs8300-v1-2-e3d13dec4233@quicinc.com> References: <20241127-dp_dts_qcs8300-v1-0-e3d13dec4233@quicinc.com> In-Reply-To: <20241127-dp_dts_qcs8300-v1-0-e3d13dec4233@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Ritesh Kumar , Yongxing Mou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732704466; l=1647; i=quic_yongmou@quicinc.com; s=20241121; h=from:subject:message-id; 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Signed-off-by: Yongxing Mou --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 7eed19a694c39dbe791afb6a991db65acb37e597..5dc855d6a22c38d97a3071d3a3d88ec551eebd1b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -35,6 +35,18 @@ sleep_clk: sleep-clk { clock-frequency = <32000>; }; }; + + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; }; &apps_rsc { @@ -223,6 +235,30 @@ &gcc { <0>; }; +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; + + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&mdss_dp0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -247,6 +283,14 @@ &rpmhcc { clock-names = "xo"; }; +&tlmm { + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; +}; + &uart7 { status = "okay"; };