| Message ID | 20241205-dp_mst-v1-28-f8618d42a99a@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | drm/msm/dp: Add MST support for MSM chipsets | expand |
On Thu, Dec 05, 2024 at 08:31:59PM -0800, Abhinav Kumar wrote: > If the DP controller is capable of supporting multiple streams > then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL > DPCD register to enable MST mode. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_display.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index e69cdfbbe10484e47475ef189849f8ff6628bd7a..033d238e956263c1212fce45aab01316ef341edb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -380,6 +380,35 @@ static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *d > return 0; > } > > +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) > +{ > + const unsigned long clear_mstm_ctrl_timeout_us = 100000; > + u8 old_mstm_ctrl; > + struct msm_dp *msm_dp = &dp->msm_dp_display; > + int ret; > + > + /* clear sink mst state */ > + drm_dp_dpcd_readb(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); > + drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, 0); > + > + /* add extra delay if MST state is not cleared */ > + if (old_mstm_ctrl) { > + drm_dbg_dp(dp->drm_dev, "MSTM_CTRL is not cleared, wait %luus\n", > + clear_mstm_ctrl_timeout_us); "is not cleared" usually means that we wrote 0 to it, but the value still stays on. Please rephrase the message, drop wait time. > + usleep_range(clear_mstm_ctrl_timeout_us, > + clear_mstm_ctrl_timeout_us + 1000); > + } > + > + ret = drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, > + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); > + if (ret < 0) { if (ret != 1) ? > + DRM_ERROR("sink mst enablement failed\n"); > + return; > + } > + > + msm_dp->mst_active = true; > +} > + > static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) > { > struct drm_connector *connector = dp->msm_dp_display.connector; > @@ -414,6 +443,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) > */ > msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); > > + if (dp->max_stream > DEFAULT_STREAM_COUNT && msm_dp_panel_read_mst_cap(dp->panel)) > + msm_dp_display_mst_init(dp); > + > msm_dp_link_reset_phy_params_vx_px(dp->link); > rc = msm_dp_ctrl_on_link(dp->ctrl, dp_display->mst_active); > if (rc) { > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index e69cdfbbe10484e47475ef189849f8ff6628bd7a..033d238e956263c1212fce45aab01316ef341edb 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -380,6 +380,35 @@ static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *d return 0; } +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) +{ + const unsigned long clear_mstm_ctrl_timeout_us = 100000; + u8 old_mstm_ctrl; + struct msm_dp *msm_dp = &dp->msm_dp_display; + int ret; + + /* clear sink mst state */ + drm_dp_dpcd_readb(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); + drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, 0); + + /* add extra delay if MST state is not cleared */ + if (old_mstm_ctrl) { + drm_dbg_dp(dp->drm_dev, "MSTM_CTRL is not cleared, wait %luus\n", + clear_mstm_ctrl_timeout_us); + usleep_range(clear_mstm_ctrl_timeout_us, + clear_mstm_ctrl_timeout_us + 1000); + } + + ret = drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink mst enablement failed\n"); + return; + } + + msm_dp->mst_active = true; +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) { struct drm_connector *connector = dp->msm_dp_display.connector; @@ -414,6 +443,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); + if (dp->max_stream > DEFAULT_STREAM_COUNT && msm_dp_panel_read_mst_cap(dp->panel)) + msm_dp_display_mst_init(dp); + msm_dp_link_reset_phy_params_vx_px(dp->link); rc = msm_dp_ctrl_on_link(dp->ctrl, dp_display->mst_active); if (rc) {
If the DP controller is capable of supporting multiple streams then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL DPCD register to enable MST mode. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/dp/dp_display.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)