| Message ID | 20241205-dp_mst-v1-43-f8618d42a99a@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | drm/msm/dp: Add MST support for MSM chipsets | expand |
On Thu, Dec 05, 2024 at 08:32:14PM -0800, Abhinav Kumar wrote: > Populate the max_streams for DP controllers to indicate MST support. > > If the pixel clock handle for the second stream fails, treat it as > SST case rather than a complete failure. Could you possibly clarify: - Are there MSM DP controllers which do not support MST? - Are there MSM DP controller which support more than 2 streams? It might be easier to to set max_streams statically rather than setting it via the descs. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 9 +++++++++ > drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 ++ > drivers/gpu/drm/msm/dp/dp_display.c | 13 ++++++++++--- > 3 files changed, 21 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index d4915a962f97b3d2a347456e197265a5dc043eb0..0e5ebcdab00936cf0ce6e35514f2932158530cc0 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -2438,6 +2438,15 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) > return 0; > } > > +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl) > +{ > + struct msm_dp_ctrl_private *ctrl; > + > + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); > + > + return ctrl->num_pixel_clks; > +} > + > struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, > struct msm_dp_panel *panel, struct drm_dp_aux *aux, > struct msm_dp_catalog *catalog, > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h > index 9ad7022d6217572395d69294c3cc4d4dbaddf0ac..f72a499809ec01a9cc5bb79762bc2604820426a1 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h > @@ -54,4 +54,6 @@ void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, > u32 start_slot, u32 tot_slots); > void msm_dp_ctrl_push_vcpf(struct msm_dp_ctrl *dp_ctrl, struct msm_dp_panel *msm_dp_panel); > > +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); > + > #endif /* _DP_CTRL_H_ */ > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index 528cda1453a85f5f8dd37bb0d2366548016c88e4..db563af19461089dbcaccce0d03fd03d5aa567aa 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -126,6 +126,7 @@ struct msm_dp_desc { > unsigned int id; > bool wide_bus_supported; > const unsigned int *intf_map; > + unsigned int max_streams; > }; > > /* to be kept in sync with enum dpu_intf of dpu_hw_mdss.h */ > @@ -149,10 +150,10 @@ static const unsigned int stream_intf_map_sa_8775p[][DP_STREAM_MAX] = { > }; > > static const struct msm_dp_desc msm_dp_desc_sa8775p[] = { > - { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true, > + { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true, .max_streams = 2, > .intf_map = stream_intf_map_sa_8775p[MSM_DP_CONTROLLER_0], > }, > - { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true, > + { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true, .max_streams = 2, > .intf_map = stream_intf_map_sa_8775p[MSM_DP_CONTROLLER_1], > }, > { .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, > @@ -1481,7 +1482,10 @@ int msm_dp_get_mst_max_stream(const struct msm_dp *dp_display) > > dp_priv = container_of(dp_display, struct msm_dp_display_private, msm_dp_display); > > - return dp_priv->max_stream; > + if (dp_priv->max_stream == msm_dp_ctrl_get_stream_cnt(dp_priv->ctrl)) > + return dp_priv->max_stream; > + else > + return DEFAULT_STREAM_COUNT; > } > > int msm_dp_mst_bridge_init(struct msm_dp *dp_display, struct drm_encoder *encoder) > @@ -1517,6 +1521,9 @@ static int msm_dp_display_probe(struct platform_device *pdev) > > dp->max_stream = DEFAULT_STREAM_COUNT; > > + if (desc->max_streams > DEFAULT_STREAM_COUNT) > + dp->max_stream = desc->max_streams; > + > dp->intf_map = desc->intf_map; > > rc = msm_dp_init_sub_modules(dp); > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index d4915a962f97b3d2a347456e197265a5dc043eb0..0e5ebcdab00936cf0ce6e35514f2932158530cc0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2438,6 +2438,15 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) return 0; } +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + return ctrl->num_pixel_clks; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct msm_dp_catalog *catalog, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 9ad7022d6217572395d69294c3cc4d4dbaddf0ac..f72a499809ec01a9cc5bb79762bc2604820426a1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -54,4 +54,6 @@ void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, u32 start_slot, u32 tot_slots); void msm_dp_ctrl_push_vcpf(struct msm_dp_ctrl *dp_ctrl, struct msm_dp_panel *msm_dp_panel); +int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); + #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 528cda1453a85f5f8dd37bb0d2366548016c88e4..db563af19461089dbcaccce0d03fd03d5aa567aa 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -126,6 +126,7 @@ struct msm_dp_desc { unsigned int id; bool wide_bus_supported; const unsigned int *intf_map; + unsigned int max_streams; }; /* to be kept in sync with enum dpu_intf of dpu_hw_mdss.h */ @@ -149,10 +150,10 @@ static const unsigned int stream_intf_map_sa_8775p[][DP_STREAM_MAX] = { }; static const struct msm_dp_desc msm_dp_desc_sa8775p[] = { - { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true, + { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true, .max_streams = 2, .intf_map = stream_intf_map_sa_8775p[MSM_DP_CONTROLLER_0], }, - { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true, + { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true, .max_streams = 2, .intf_map = stream_intf_map_sa_8775p[MSM_DP_CONTROLLER_1], }, { .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, @@ -1481,7 +1482,10 @@ int msm_dp_get_mst_max_stream(const struct msm_dp *dp_display) dp_priv = container_of(dp_display, struct msm_dp_display_private, msm_dp_display); - return dp_priv->max_stream; + if (dp_priv->max_stream == msm_dp_ctrl_get_stream_cnt(dp_priv->ctrl)) + return dp_priv->max_stream; + else + return DEFAULT_STREAM_COUNT; } int msm_dp_mst_bridge_init(struct msm_dp *dp_display, struct drm_encoder *encoder) @@ -1517,6 +1521,9 @@ static int msm_dp_display_probe(struct platform_device *pdev) dp->max_stream = DEFAULT_STREAM_COUNT; + if (desc->max_streams > DEFAULT_STREAM_COUNT) + dp->max_stream = desc->max_streams; + dp->intf_map = desc->intf_map; rc = msm_dp_init_sub_modules(dp);
Populate the max_streams for DP controllers to indicate MST support. If the pixel clock handle for the second stream fails, treat it as SST case rather than a complete failure. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 9 +++++++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 ++ drivers/gpu/drm/msm/dp/dp_display.c | 13 ++++++++++--- 3 files changed, 21 insertions(+), 3 deletions(-)