From patchwork Fri Dec 13 09:52:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashanth K X-Patchwork-Id: 13906770 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A24611B4C35; Fri, 13 Dec 2024 09:53:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734083629; cv=none; b=GYW+tpKQCAcC5afZVLtfwjyJpbdIIkZIgp7TvIdpIHuFb0BEf7/YkFpW4AwmafafpGcPuFuE/WkhqpDouaYq59cO3YNrsAHyDWsn1mDAYA9rJh5mvsTaRUi057x6t46J//3AdFyptyiWB1ptIfC7sT56RBSxHqlQ/U/pM5kTD1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734083629; c=relaxed/simple; bh=FaZ1hzMHdog/Cu4XFuQZtxdwcnJmetXamNFTGvr4Jsk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N9GX0iAo1okcCai3/FUMzQRlynF6AukaFPWFuQ/DlUTg4rVjcc/OSxpfzJe7sqmbhU9MeJ2CEppDUeT+hI4hKixecYU/GUCOfI0gm0zhZlJEg23cene3Q0ANeYfPRXh8YQDwv5+6Qv/2zYxNpiDTBSIOK+ZXrlBGWeH9U17UJGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=KOgFLEIY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KOgFLEIY" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BD3cJW3016584; Fri, 13 Dec 2024 09:53:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QQr9fctH+5XBxgpgp99EKbAUFidxNgaGD8AtVTfp4I4=; b=KOgFLEIYF61dqYTg V1SJFZXLywWEHF+vVWJwD3pZNhX5tuh0gTuJr29xhmvWr3FfrwBA7/Kpqu4fXCcY sJnpoX+2tf0IPSDHHPdRNEia9USWxQfBDxH0BgZMiZue8D7LOZIRfW3zDsy1Ekiw tltTtKgKRQ2HSs8fK4wHbGSkj6G0rcPnyme8B3p2cy1/A21SpGNCvCVkQDs8E2AQ MEFVjXOtfWhFmXJ3yZhse+O22VaQRbFmezcYRObWFNKtIff8/fX6Ub8zrXYw8C38 qEGCW4/hKcTbwdpx2D9eMa6Q4TJuu2NsQ3slAGZg/0/cROIYSaeHFjUtRp863zLG 2UPaug== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43fxw4u5hx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 09:53:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BD9rhco028900 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 09:53:43 GMT Received: from hu-prashk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 01:53:39 -0800 From: Prashanth K To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Kurapati CC: , , , , Prashanth K Subject: [PATCH v2 13/19] ARM: dts: qcom: Disable USB U1/U2 entry for SDX55 Date: Fri, 13 Dec 2024 15:22:31 +0530 Message-ID: <20241213095237.1409174-14-quic_prashk@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213095237.1409174-1-quic_prashk@quicinc.com> References: <20241213095237.1409174-1-quic_prashk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BvGT420-i8eCoIxep06RMLaoFRadSSbu X-Proofpoint-GUID: BvGT420-i8eCoIxep06RMLaoFRadSSbu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=467 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130067 Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. 3. On targets like SDX75, intermittent disconnects were observed with certain cables due to impedence variations. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index d0f6120b665d..f431cdfbbc3d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -613,6 +613,8 @@ usb_dwc3: usb@a600000 { iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; };