From patchwork Fri Dec 13 09:52:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashanth K X-Patchwork-Id: 13906760 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A30BD1B85D2; Fri, 13 Dec 2024 09:53:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734083589; cv=none; b=mupOmp3S/JUBAKxPPthzKR1KEL5Zk2MTtD8x1mlrk6YfMUFHAmmbQaxTeAG5Pz/VnMqhi8yi2YB62f3k9HB3IQMsbgNPdXK9aqdMop9LSzW0VOkJyGM0g9bbO5p5dkMmTnqLoBeOQG1fCeW/o+BY8MGALGnkDSIJNs6ZxIYziRs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734083589; c=relaxed/simple; bh=kiyXkb3V8nAFE11cuAv8cHd55oZ5x9Zkyl0hixMM2gM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fh7lqdNteAH+gtD6vUGK53szUHzasA3ic3js/m9717LeZIP4XzhwVKqDLSMW/k/VYJi7WqcxR5ubjJmKjieE8ENvqLouSJXzVn5/SPYC6aZVUEQkuqgTA/Nw/mfV7b0TFRi+42zw5G8fDILRJirMuamEGrqmUky+iF7GLYStE3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=TGG5I6gx; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="TGG5I6gx" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BD9pMn8018942; Fri, 13 Dec 2024 09:53:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= d08adz+4bDN4JmKBzyHtZlczB05OYOZKKkihVU99sks=; b=TGG5I6gx8EmuBHz/ oB9qpvpW2ycy97DX4FM8mOGEJwzmTEz0sp31Q+AAjNvXzPcko2LVUdv7smS1cTyf sBeV+Gj99nEpQa1MkLAKjC800Ua/lX85U560sgClPwO3vmpSA3ly9BXo6JCeBXcB o1MFnumSx29nRIPcplcAP31lnHNV8AgD2Zfvw6BIt/abkkfXqqBVS5XmpDJpO6g1 FLL9qY8dHaJPX7gT7y64GZgTrWIaWHRaCrK4vcJ56AaiVrHSGLupZwHLKa9GiouW kNvSDTiT1QPMP1ODDcRFG/zGLvohxkbgYBoObwUngcsZIBo3SksQM6IevFFhdSeR Lfzt4g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43gjnb004f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 09:53:04 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BD9r3d1009134 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 09:53:03 GMT Received: from hu-prashk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 01:53:00 -0800 From: Prashanth K To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Kurapati CC: , , , , Prashanth K Subject: [PATCH v2 03/19] arm64: dts: qcom: Disable USB U1/U2 entry for SM8150 Date: Fri, 13 Dec 2024 15:22:21 +0530 Message-ID: <20241213095237.1409174-4-quic_prashk@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213095237.1409174-1-quic_prashk@quicinc.com> References: <20241213095237.1409174-1-quic_prashk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CJ4GjdvMTXHfy7HTA_K6CGTdKV-nT9zf X-Proofpoint-GUID: CJ4GjdvMTXHfy7HTA_K6CGTdKV-nT9zf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 phishscore=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=469 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130067 From: Krishna Kurapati Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati Signed-off-by: Prashanth K --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index cedae8d03a51..4dbda54b47a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3658,6 +3658,8 @@ usb_1_dwc3: usb@a600000 { iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; @@ -3735,6 +3737,8 @@ usb_2_dwc3: usb@a800000 { iommus = <&apps_smmu 0x160 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; };