From patchwork Tue Dec 31 08:11:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashanth K X-Patchwork-Id: 13923681 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BD21AB51F; Tue, 31 Dec 2024 08:12:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735632753; cv=none; b=txUKR0RDZ34rtVtbO9+Q3y0i3IAbEwLOyDg4mcNnXlKN5Qj1l3CIsVU1rkdQ4GzNT6ZfdSUdyLxSgh9q7yLP6toLMWrgUzOUP+tb2bFI3/Bn6SSbqKxXTVa3qy2DKUWfqIrerduwMWjoKe7iRLeP1GyHpGWI52w+EDZRfedbwQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735632753; c=relaxed/simple; bh=V/f9L9ihRckHmzfTdCR2ME3XKwZbm2xX3urmhS410tk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W6HRHqYo2u31ZLNRdlLjdoUdFRQNACFKusvkYjS578dZs/tlUWZoTflIFljehbMtHIDWTAHgtlw/jxRtJicmdAcEwK/QqcRsJORNx6ohRqyW5B72W15WTcEGyzaQvs4PzCkpZiP+UNQuoIxVNoW8knUcK05kW4dx4RJ/qbSzfyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=a0H4ztUG; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="a0H4ztUG" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BUHsVBS018019; Tue, 31 Dec 2024 08:12:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kXEnF3FnyUMs8TPwAxpi1m0/qeLWYWYavwWlVzLtmKc=; b=a0H4ztUGI2+IxBjm Cnk4O+h6Ga9ywp30K/RNqbIqPrbT+R8BmUICP2MV9vwwaCZUjFDKxfQgiy2/Sjjz SDSyW6pTF/l/1ZxmBJKkZ2s4OoGlmaJl9JOCdMuFqZwjPOdcnyxCWVbPJYaW+wFp 4odHcGxbF+ObE6P9bgd6ba2VDYeDHTnGdjnn9gc4CGmXyv97N4AkJnN7HM/7kiX6 XCYGyLMz4PVLXWMhbG1s4uzdNMF7cwfiksu14Wj89KTjiYzF6fRZxtxoo34KqWZC 5pkXnp7oWkXbi92U4OVQNbmrDn3aivzY+gaLqolLEIvxr7tRy75x9qraD1HweRqL yOmIUA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43v0aq1bft-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Dec 2024 08:12:28 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BV8CSME013429 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Dec 2024 08:12:28 GMT Received: from hu-prashk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 31 Dec 2024 00:12:24 -0800 From: Prashanth K To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Kurapati CC: , , , , Prashanth K , Konrad Dybcio Subject: [PATCH v4 14/17] arm64: dts: qcom: x1e80100: Disable USB U1/U2 entry Date: Tue, 31 Dec 2024 13:41:12 +0530 Message-ID: <20241231081115.3149850-15-quic_prashk@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241231081115.3149850-1-quic_prashk@quicinc.com> References: <20241231081115.3149850-1-quic_prashk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: P_kxwL9eaY5s_HRICZ-Busqpp4-KSYWJ X-Proofpoint-GUID: P_kxwL9eaY5s_HRICZ-Busqpp4-KSYWJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 suspectscore=0 adultscore=0 impostorscore=0 clxscore=1015 mlxlogscore=455 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412310068 Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 88805629ed2b..d522255bb249 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4063,6 +4063,8 @@ usb_1_ss2_dwc3: usb@a000000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent; @@ -4151,6 +4153,8 @@ usb_2_dwc3: usb@a200000 { phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; ports { #address-cells = <1>; @@ -4247,6 +4251,8 @@ usb_mp_dwc3: usb@a400000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent; }; @@ -4318,6 +4324,8 @@ usb_1_ss0_dwc3: usb@a600000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent; @@ -4418,6 +4426,8 @@ usb_1_ss1_dwc3: usb@a800000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent;