| Message ID | 20250103063708.3256467-3-quic_mmanikan@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 70c325ef6c979e5308edd7ef04077ceb6659d340 |
| Headers | show |
| Series | Add SPI support for IPQ5424 | expand |
On 3.01.2025 7:37 AM, Manikanta Mylavarapu wrote: > Enable the SPI0 node and configure the associated gpio pins. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > --- > Changes in V4: > - Revert the 'renaming of spi0 to spi4' and follow the existing > naming convention such as spi0 and spi1. > - Update commit message. > > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 43 +++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > index d4d31026a026..60cfa8708eb4 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > @@ -23,6 +23,36 @@ &sleep_clk { > }; > > &tlmm { > + spi0_default_state: spi0-default-state { > + clk-pins { > + pins = "gpio6"; > + function = "spi0_clk"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + > + cs-pins { > + pins = "gpio7"; > + function = "spi0_cs"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + miso-pins { > + pins = "gpio8"; > + function = "spi0_miso"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + > + mosi-pins { > + pins = "gpio9"; > + function = "spi0_mosi"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + }; > + > sdc_default_state: sdc-default-state { > clk-pins { > pins = "gpio5"; > @@ -57,3 +87,16 @@ &xo_board { > clock-frequency = <24000000>; > }; > > +&spi0 { 's' < 't', please re-sort this alphabetically Konrad
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index d4d31026a026..60cfa8708eb4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -23,6 +23,36 @@ &sleep_clk { }; &tlmm { + spi0_default_state: spi0-default-state { + clk-pins { + pins = "gpio6"; + function = "spi0_clk"; + drive-strength = <8>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio7"; + function = "spi0_cs"; + drive-strength = <8>; + bias-pull-up; + }; + + miso-pins { + pins = "gpio8"; + function = "spi0_miso"; + drive-strength = <8>; + bias-pull-down; + }; + + mosi-pins { + pins = "gpio9"; + function = "spi0_mosi"; + drive-strength = <8>; + bias-pull-down; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio5"; @@ -57,3 +87,16 @@ &xo_board { clock-frequency = <24000000>; }; +&spi0 { + pinctrl-0 = <&spi0_default_state>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +};
Enable the SPI0 node and configure the associated gpio pins. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- Changes in V4: - Revert the 'renaming of spi0 to spi4' and follow the existing naming convention such as spi0 and spi1. - Update commit message. arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 43 +++++++++++++++++++++ 1 file changed, 43 insertions(+)