From patchwork Tue Jan 7 10:16:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gokul Sriram P (QUIC)" X-Patchwork-Id: 13928625 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2501E7668; Tue, 7 Jan 2025 10:17:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736245045; cv=none; b=s1rnqWyqhSLQFJM2iHAn+kN4m/AnDLvQxWI3IMPFH0Q0+3BI0fRD6XY8hiAb8hGWF+qy7lhiKRPe1Ms8q31KmoQeWfcwrgGzyMiBptUGTGTfwETDsN5FKppUpJxyYdyuqDKFrPlg/n1RG/Zaj/hO8Jd2lwMj9PWJ3AAStyd4ALs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736245045; c=relaxed/simple; bh=3AoGROO8eRM/89r7uGVMpJ9BSFfY9ZXpZljaSw/2wA8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dCtpqOWJZHC/qu75zY7tWMG1pGN5q0Ea6nW46bS7I+Tr3o8pfdU059hfKCyqaMCHJCdV51TXTkzKLQruBME5WL8VV/A31fpekvfjPMz8ZHSlfYlbbKKTGlppSGBVtIjKjuPzLuiQlSc9pLcTlNhV7RkZ67bhfON5S+Odxlt4FU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ImIhnbx7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ImIhnbx7" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5077pV5m006257; Tue, 7 Jan 2025 10:17:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= m9RktyqKbWQzh/I8wuRG0qcjil056rytstZtZrs/Nf8=; b=ImIhnbx7cx8p7WVQ 9k1Y0M7q0ck8g+5UIR43eULdp/ZNoNgRO/5Us1SwhlEUrcZZ5xspvEnwvJLhpk6m luY47EQBwoJaDKzfk5jQuTBeNBcj1mSZjoKL1JD5GiWkIyMLxlIKtxK7WH1rr6f7 h+3hj+s+kPPlA5sKyedieCwApcMggvnrZSTlcIz8/irKGCDPzVc0OdxMYtJQdD/V zAG1d6tlDf709hFJKv+toRRqvTzEG5E1sNyVTBxsa05LIOu4aMXFMqvM99j7NMhb xrH7dN+JEqtW4XPWRjsf/7LYODYhGdF2ZMs6OEwzGTtWHmINRjMAfKNZsVBGF8rx tSMM/Q== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44108fgb3g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jan 2025 10:17:17 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 507AHGrj028916 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Jan 2025 10:17:16 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 7 Jan 2025 02:17:11 -0800 From: Gokul Sriram Palanisamy To: , , , , , , , , , , , , CC: , , Subject: [PATCH V3 1/8] firmware: qcom_scm: ipq5332: add support to pass metadata size Date: Tue, 7 Jan 2025 15:46:40 +0530 Message-ID: <20250107101647.2087358-2-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250107101647.2087358-1-quic_gokulsri@quicinc.com> References: <20250107101647.2087358-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MjVd8RwmEQoAXAT037ov7RfvwhuyzgJb X-Proofpoint-GUID: MjVd8RwmEQoAXAT037ov7RfvwhuyzgJb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 priorityscore=1501 clxscore=1011 mlxscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501070085 From: Manikanta Mylavarapu IPQ5332 security software running under trustzone requires metadata size. With new command support added in TrustZone that includes a size parameter, pass metadata size as well. This new command is specific to IPQ5332 SoC. Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy --- drivers/firmware/qcom/qcom_scm.c | 13 +++++++++++-- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 72bf87ddcd96..a713788926b0 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -580,8 +580,6 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, int ret; struct qcom_scm_desc desc = { .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, - .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), .args[0] = peripheral, .owner = ARM_SMCCC_OWNER_SIP, }; @@ -616,6 +614,17 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, desc.args[1] = mdata_phys; + if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_PAS_INIT_IMAGE_V2)) { + desc.cmd = QCOM_SCM_PAS_INIT_IMAGE_V2; + desc.arginfo = + QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL); + desc.args[2] = size; + } else { + desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE; + desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); + } + ret = qcom_scm_call(__scm->dev, &desc, &res); qcom_scm_bw_disable(); diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index e36b2f67607f..9aad9f92517f 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -96,6 +96,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_PIL 0x02 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 +#define QCOM_SCM_PAS_INIT_IMAGE_V2 0x1a #define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02 #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05 #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06