| Message ID | 20250107101647.2087358-7-quic_gokulsri@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add new driver for WCSS secure PIL loading | expand |
On Tue, Jan 07, 2025 at 03:46:45PM +0530, Gokul Sriram Palanisamy wrote: > From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > > Enable nodes required for q6 remoteproc bring up. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 64 ++++++++++++++++++++++++++- > 1 file changed, 63 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index d3c3e215a15c..85e10b20342a 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -2,7 +2,7 @@ > /* > * IPQ5332 device tree source > * > - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #include <dt-bindings/clock/qcom,apss-ipq.h> > @@ -146,6 +146,11 @@ smem@4a800000 { > > hwlocks = <&tcsr_mutex 3>; > }; > + > + q6_region: wcss@4a900000 { > + reg = <0x0 0x4a900000 0x0 0x2b00000>; > + no-map; > + }; > }; > > soc@0 { > @@ -479,6 +484,39 @@ frame@b128000 { > status = "disabled"; > }; > }; > + > + q6v5_wcss: remoteproc@d100000 { > + compatible = "qcom,ipq5332-wcss-sec-pil"; > + reg = <0xd100000 0x4040>; > + firmware-name = "ath12k/IPQ5332/hw1.0/q6_fw0.mdt"; If the device is fused to use vendor keys, will the same firmware image work? If not, the remoteproc should be disabled by default and the firmware-name should go to the board file. And anyway, please use .mbn > + interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>, > + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, > + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, > + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, > + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; >
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3c3e215a15c..85e10b20342a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -2,7 +2,7 @@ /* * IPQ5332 device tree source * - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <dt-bindings/clock/qcom,apss-ipq.h> @@ -146,6 +146,11 @@ smem@4a800000 { hwlocks = <&tcsr_mutex 3>; }; + + q6_region: wcss@4a900000 { + reg = <0x0 0x4a900000 0x0 0x2b00000>; + no-map; + }; }; soc@0 { @@ -479,6 +484,39 @@ frame@b128000 { status = "disabled"; }; }; + + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5332-wcss-sec-pil"; + reg = <0xd100000 0x4040>; + firmware-name = "ath12k/IPQ5332/hw1.0/q6_fw0.mdt"; + interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_IM_SLEEP_CLK>; + clock-names = "sleep"; + + qcom,smem-states = <&wcss_smp2p_out 1>, + <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; }; timer { @@ -488,4 +526,28 @@ timer { <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; };