| Message ID | 20250107135624.7628-1-quic_rdwivedi@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [V9] scsi: ufs: qcom: Enable UFS Shared ICE Feature | expand |
Hi Ram, kernel test robot noticed the following build errors: [auto build test ERROR on jejb-scsi/for-next] [also build test ERROR on mkp-scsi/for-next mani-mhi/mhi-next linus/master v6.13-rc6 next-20250107] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Ram-Kumar-Dwivedi/scsi-ufs-qcom-Enable-UFS-Shared-ICE-Feature/20250107-220209 base: https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git for-next patch link: https://lore.kernel.org/r/20250107135624.7628-1-quic_rdwivedi%40quicinc.com patch subject: [PATCH V9] scsi: ufs: qcom: Enable UFS Shared ICE Feature config: arm64-randconfig-001-20250108 (https://download.01.org/0day-ci/archive/20250108/202501081935.NGoKgB9p-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250108/202501081935.NGoKgB9p-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202501081935.NGoKgB9p-lkp@intel.com/ All error/warnings (new ones prefixed by >>): drivers/ufs/host/ufs-qcom.c: In function 'ufs_qcom_set_host_caps': >> drivers/ufs/host/ufs-qcom.c:968:31: error: 'UFS_QCOM_CAP_ICE_CONFIG' undeclared (first use in this function) 968 | host->caps |= UFS_QCOM_CAP_ICE_CONFIG; | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/ufs/host/ufs-qcom.c:968:31: note: each undeclared identifier is reported only once for each function it appears in drivers/ufs/host/ufs-qcom.c: At top level: >> drivers/ufs/host/ufs-qcom.c:223:13: warning: 'ufs_qcom_config_ice_allocator' defined but not used [-Wunused-function] 223 | static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +/UFS_QCOM_CAP_ICE_CONFIG +968 drivers/ufs/host/ufs-qcom.c 962 963 static void ufs_qcom_set_host_caps(struct ufs_hba *hba) 964 { 965 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 966 967 if (host->hw_ver.major >= 0x5) > 968 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; 969 } 970
On Tue, Jan 07, 2025 at 07:26:24PM +0530, Ram Kumar Dwivedi wrote: > By default, the UFS controller allocates a fixed number of RX > and TX engines statically. Consequently, when UFS reads are in > progress, the TX ICE engines remain idle, and vice versa. > This leads to inefficient utilization of RX and TX engines. > > To address this limitation, enable the UFS shared ICE feature for > Qualcomm UFS V5.0 and above. This feature utilizes a pool of crypto > cores for both TX streams (UFS Write – Encryption) and RX streams > (UFS Read – Decryption). With this approach, crypto cores are > dynamically allocated to either the RX or TX stream as needed. > > Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> > --- > Changes from v8: > 1. Addressed Manivannan's comment to call ufs_qcom_config_ice_allocator() > from ufs_qcom_ice_enable(). No I did not. More below. > 2. Addressed Manivannan's comment to place UFS_QCOM_CAP_ICE_CONFIG > definition outside of the ufs_qcom_host struct. > 3. Addressed Manivannan's comment to align ICE definitions with > other definitions. > > Changes from v7: > 1. Addressed Eric's comment to perform ice configuration only if > UFSHCD_CAP_CRYPTO is enabled. > > Changes from v6: > 1. Addressed Eric's comment to replace is_ice_config_supported() helper > function with a conditional check for UFS_QCOM_CAP_ICE_CONFIG. > > Changes from v5: > 1. Addressed Bart's comment to declare the "val" variable with > the "static" keyword. > > Changes from v4: > 1. Addressed Bart's comment to use get_unaligned_le32() instead of > bit shifting and to declare val with the const keyword. > > Changes from v3: > 1. Addressed Bart's comment to change the data type of "config" to u32 > and "val" to uint8_t. > > Changes from v2: > 1. Refactored the code to have a single algorithm in the code and > enabled by default. > 2. Revised the commit message to incorporate the refactored change. > 3. Qcom host capabilities are now enabled in a separate function. > > Changes from v1: > 1. Addressed Rob's and Krzysztof's comment to fix dt binding compilation > issue. > 2. Addressed Rob's comment to enable the nodes in example. > 3. Addressed Eric's comment to rephrase patch commit description. > Used terminology as ICE allocator instead of ICE algorithm. > 4. Addressed Christophe's comment to align the comment as per kernel doc. > --- > drivers/ufs/host/ufs-qcom.c | 38 +++++++++++++++++++++++++++++++++ > drivers/ufs/host/ufs-qcom.h | 42 ++++++++++++++++++++++++++++++++++++- > 2 files changed, 79 insertions(+), 1 deletion(-) > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c > index 68040b2ab5f8..f4b9fb0740b4 100644 > --- a/drivers/ufs/host/ufs-qcom.c > +++ b/drivers/ufs/host/ufs-qcom.c > @@ -15,6 +15,7 @@ > #include <linux/platform_device.h> > #include <linux/reset-controller.h> > #include <linux/time.h> > +#include <linux/unaligned.h> > > #include <soc/qcom/ice.h> > > @@ -105,11 +106,33 @@ static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) > } > > #ifdef CONFIG_SCSI_UFS_CRYPTO > +/** > + * ufs_qcom_config_ice_allocator() - ICE core allocator configuration > + * > + * @host: pointer to qcom specific variant structure. > + */ > +static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) > +{ > + struct ufs_hba *hba = host->hba; > + static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; > + u32 config; > + > + if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || > + !(host->hba->caps & UFSHCD_CAP_CRYPTO)) > + return; > + > + config = get_unaligned_le32(val); > + > + ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); > + ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); > +} > > static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) > { > if (host->hba->caps & UFSHCD_CAP_CRYPTO) > qcom_ice_enable(host->ice); > + > + ufs_qcom_config_ice_allocator(host); I did not ask you to move ufs_qcom_config_ice_allocator() inside ufs_qcom_ice_enable(). Rather do below in ufs_qcom_hce_enable_notify(): ufs_qcom_config_ice_allocator(host); ufs_qcom_ice_enable(host); > } > > static int ufs_qcom_ice_init(struct ufs_qcom_host *host) > @@ -196,6 +219,11 @@ static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) > { > return 0; > } > + > +static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) > +{ > +} > + > #endif > > static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) > @@ -932,6 +960,14 @@ static void ufs_qcom_set_host_params(struct ufs_hba *hba) > host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); > } > > +static void ufs_qcom_set_host_caps(struct ufs_hba *hba) > +{ > + struct ufs_qcom_host *host = ufshcd_get_variant(hba); > + > + if (host->hw_ver.major >= 0x5) > + host->caps |= UFS_QCOM_CAP_ICE_CONFIG; > +} > + > static void ufs_qcom_set_caps(struct ufs_hba *hba) > { > hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; > @@ -940,6 +976,8 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) > hba->caps |= UFSHCD_CAP_WB_EN; > hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; > hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; > + > + ufs_qcom_set_host_caps(hba); > } > > /** > diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h > index b9de170983c9..de41028ecee0 100644 > --- a/drivers/ufs/host/ufs-qcom.h > +++ b/drivers/ufs/host/ufs-qcom.h > @@ -135,6 +135,46 @@ enum { > #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 > #define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 > > + Extra newline > +#ifdef CONFIG_SCSI_UFS_CRYPTO As I said in previous iteration, you do not need the guard for definitions. > + > +/* ICE configuration to share AES engines among TX stream and RX stream */ > +#define UFS_QCOM_CAP_ICE_CONFIG BIT(0) This is a bit definition. So define this as like other bit definitions in this header. > +#define ICE_ALLOCATOR_TYPE 2 > +#define REG_UFS_MEM_ICE_CONFIG 0x260C > +#define REG_UFS_MEM_ICE_NUM_CORE 0x2664 I asked you to move these two register definitions to register enum but still not addressed. > + > +/* > + * Number of cores allocated for RX stream when Read data block received and > + * Write data block is not in progress > + */ > +#define NUM_RX_R1W0 28 > + > +/* > + * Number of cores allocated for TX stream when Device asked to send write > + * data block and Read data block is not in progress > + */ > +#define NUM_TX_R0W1 28 > + > +/* > + * Number of cores allocated for RX stream when Read data block received and > + * Write data block is in progress > + * OR > + * Device asked to send write data block and Read data block is in progress > + */ > +#define NUM_RX_R1W1 15 > + > +/* > + * Number of cores allocated for TX stream (UFS write) when Read data block > + * received and Write data block is in progress > + * OR > + * Device asked to send write data block and Read data block is in progress > + */ > +#define NUM_TX_R1W1 13 > + > +#endif /* UFS_CRYPTO */ > + Extra newline. - Mani
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 68040b2ab5f8..f4b9fb0740b4 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -15,6 +15,7 @@ #include <linux/platform_device.h> #include <linux/reset-controller.h> #include <linux/time.h> +#include <linux/unaligned.h> #include <soc/qcom/ice.h> @@ -105,11 +106,33 @@ static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) } #ifdef CONFIG_SCSI_UFS_CRYPTO +/** + * ufs_qcom_config_ice_allocator() - ICE core allocator configuration + * + * @host: pointer to qcom specific variant structure. + */ +static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) +{ + struct ufs_hba *hba = host->hba; + static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; + u32 config; + + if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || + !(host->hba->caps & UFSHCD_CAP_CRYPTO)) + return; + + config = get_unaligned_le32(val); + + ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); + ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); +} static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) { if (host->hba->caps & UFSHCD_CAP_CRYPTO) qcom_ice_enable(host->ice); + + ufs_qcom_config_ice_allocator(host); } static int ufs_qcom_ice_init(struct ufs_qcom_host *host) @@ -196,6 +219,11 @@ static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) { return 0; } + +static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) +{ +} + #endif static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) @@ -932,6 +960,14 @@ static void ufs_qcom_set_host_params(struct ufs_hba *hba) host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); } +static void ufs_qcom_set_host_caps(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + if (host->hw_ver.major >= 0x5) + host->caps |= UFS_QCOM_CAP_ICE_CONFIG; +} + static void ufs_qcom_set_caps(struct ufs_hba *hba) { hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; @@ -940,6 +976,8 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) hba->caps |= UFSHCD_CAP_WB_EN; hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; + + ufs_qcom_set_host_caps(hba); } /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index b9de170983c9..de41028ecee0 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -135,6 +135,46 @@ enum { #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 #define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 + +#ifdef CONFIG_SCSI_UFS_CRYPTO + +/* ICE configuration to share AES engines among TX stream and RX stream */ +#define UFS_QCOM_CAP_ICE_CONFIG BIT(0) +#define ICE_ALLOCATOR_TYPE 2 +#define REG_UFS_MEM_ICE_CONFIG 0x260C +#define REG_UFS_MEM_ICE_NUM_CORE 0x2664 + +/* + * Number of cores allocated for RX stream when Read data block received and + * Write data block is not in progress + */ +#define NUM_RX_R1W0 28 + +/* + * Number of cores allocated for TX stream when Device asked to send write + * data block and Read data block is not in progress + */ +#define NUM_TX_R0W1 28 + +/* + * Number of cores allocated for RX stream when Read data block received and + * Write data block is in progress + * OR + * Device asked to send write data block and Read data block is in progress + */ +#define NUM_RX_R1W1 15 + +/* + * Number of cores allocated for TX stream (UFS write) when Read data block + * received and Write data block is in progress + * OR + * Device asked to send write data block and Read data block is in progress + */ +#define NUM_TX_R1W1 13 + +#endif /* UFS_CRYPTO */ + + static inline void ufs_qcom_get_controller_revision(struct ufs_hba *hba, u8 *major, u16 *minor, u16 *step) @@ -196,7 +236,7 @@ struct ufs_qcom_host { #ifdef CONFIG_SCSI_UFS_CRYPTO struct qcom_ice *ice; #endif - + u32 caps; void __iomem *dev_ref_clk_ctrl_mmio; bool is_dev_ref_clk_enabled; struct ufs_hw_version hw_ver;