From patchwork Wed Jan 8 05:58:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13930151 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 913911A23BF; Wed, 8 Jan 2025 05:59:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736315963; cv=none; b=h1SbI3u0Gj4/JLtOjiVwtDC5eMSeYuYwbPjt9RHZWbLuwYFh5iZIZKIXyzcx3HDnd6z7CaknFgSyjlXBY94yBsb6q9btKqemZuqw9kR4ZQdfyQf090yjIbcFAd7qBFHG9ROtbyQfYXe0Cg6uVWUZhzv1gSn7GRX0Z/RF/nZ8/Cc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736315963; c=relaxed/simple; bh=9DSzZN6xo2Iq9LJAy20g2EsTPVNvT9ZBn/Lz60Ynm/g=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N1yhfc7TquLxqQsx/iJX4XHc7f30tsOeFflHfmIPX2MTjJ/Vntpp3JxLY3FC7rM2Ywshz0ZtKJ3lbZjO5xWssuF13vz9AcYVmSYz+iFfMPua+9lWeWUgHfp7KaHTK2vDuiKn4rFrzcfxTsFwGnCivDbJyw1FpXBfWFtkFjd4ltw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=X84OQM3N; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="X84OQM3N" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50802SWk008841; Wed, 8 Jan 2025 05:59:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bDwwdQrAF+o2ZgCJKQl/Co20Ro5PRpLLEom9hcdJq6s=; b=X84OQM3NlCUioybM rWElZUS0AxY5u6L6ojd1M+yXxA9ggI+u/6DhTwkPB0TFf1ECZVVtdw5mFM9PFvW5 25ajFHLxKdSWbc/mwzwUbX2ZXyYVuqIGTcS37sUKgWKdxSEdJDiJK2hKK4VPn72m YesPVbmjoKczSdBcBWpK/7pnw1gQNePECcMM1PwExY8NbbkFyOWWimurP5d4oiiD L3KuwR5gDbL1+SCSkntXnVg2eZkr/TjGmQiIIBGNZqo+LV7qYDzxvI+hv4Crpd9P se1J9eQh2ZnybB2v5Z5IY5G+NLq8aOcFx0uRnNxfx+tjdcTVPi1+OvAUJRAgHzN5 O1wz6Q== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 441efm0puq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Jan 2025 05:59:06 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5085x6K9016841 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Jan 2025 05:59:06 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 7 Jan 2025 21:59:00 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 1/5] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy Date: Wed, 8 Jan 2025 11:28:38 +0530 Message-ID: <20250108055842.2042876-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108055842.2042876-1-quic_varada@quicinc.com> References: <20250108055842.2042876-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0mQEXuLvEeBBMNCk0-GzsHpIN1AQNzIb X-Proofpoint-ORIG-GUID: 0mQEXuLvEeBBMNCk0-GzsHpIN1AQNzIb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 phishscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501080046 From: Nitheesh Sekar Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. Signed-off-by: Nitheesh Sekar Signed-off-by: Varadarajan Narayanan --- v6: * Fix num-lanes definition * Make it mandatory v5: * Drop '3x1' & '3x2' from compatible string * Use 'num-lanes' to differentiate instead of '3x1' or '3x2' in compatible string * Describe clocks and resets instead of just maxItems v4: Remove reset-names as the resets are not used individually Remove clock-output-names as its usage is removed from driver Fix order in the 'required' section v3: Fix compatible string to be similar to other phys and rename file accordingly Fix clocks minItems -> maxItems Change one of the maintainer from Sricharan to Varadarajan v2: Rename the file to match the compatible Drop 'driver' from title Dropped 'clock-names' Fixed 'reset-names' --- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml new file mode 100644 index 000000000000..bdecae76692c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar + - Varadarajan Narayanan + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + +properties: + compatible: + enum: + - qcom,ipq5332-uniphy-pcie-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + + resets: + items: + - description: phy reset + - description: ahb reset + - description: cfg reset + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + num-lanes: + enum: [1, 2] + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + - "#clock-cells" + - num-lanes + +additionalProperties: false + +examples: + - | + #include + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + + num-lanes = <1>; + };