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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5428bec06e1sm73866e87.191.2025.01.08.20.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 20:35:52 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 09 Jan 2025 06:35:45 +0200 Subject: [PATCH v4 1/5] nvmem: core: fix bit offsets of more than one byte Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250109-sar2130p-nvmem-v4-1-633739fe5f11@linaro.org> References: <20250109-sar2130p-nvmem-v4-0-633739fe5f11@linaro.org> In-Reply-To: <20250109-sar2130p-nvmem-v4-0-633739fe5f11@linaro.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Akhil P Oommen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=28lfeP0elk+tC/FtwJpVo5ll99ssX0YY1tno5A6BThw=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnf1IjOYS2hG2FXUXbR7hTDfuUum1vNcR6hSs2u 0caXs+FDT2JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ39SIwAKCRAU23LtvoBl uHVeD/9UumRB6poWTUCyfIZtKnmWF+AJy9MH2f3Do2WizXmDzFk4eUe+J4CIiqGvAIC4TXLRkkd EhK1+bETRA2IZKUvIjpwVj4j90Ee9DM6PKfH7UMIr3qH7nSibGnDoVeqF0zHs2OOT8fPzPIRkc1 NazeYfz2O0RsIRUyEkp/ExPbargr2iYPg+rT7/MLa2k52S0OQh+KcjJ2Py5gatggYzBHEC348gx eENbyNOmrHC4PqEBzf4eBh1caw8jcDacmQJo/ueWp9NNbIHaR2OX0jkH4JWZ2Z4zkOdXpa9s3Pg OFrIcGjW6sOrWVfDw/YtCEwLgrO2B2s+m6AkdrvTMjk9rzIi27FQ3cM9WA5doFyguC5fYCeM4Op WLtIbzjNawxE3XUJDfTKpRGQWyKHXuCojiQ5C6T277EbWjC61hwrw6jsedr8nbz0fvsEIH/OymX aXdFeGlFQXfqh8uNkYxsGxeyfeBqs+OohHDqmPQbzlySYG22kVKG9P2MEf9l1I+2UB9NbQyRJYA hYykNLoMVrIbCi9tR/9wLorq2KeKJbySZvU3sCOp7dWbfZyGgXRNmJgFxGfQaeXO9c7KsjAgc5s A5JXCguP2ou5fwaxuZXazHPl48xSkZCgJNT1h0+tqtr54nJz1ZwKyd1luMy+r73xXV909Tl9j4K FcoxU8hCJfgWanA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A If the NVMEM specifies a stride to access data, reading particular cell might require bit offset that is bigger than one byte. Rework NVMEM core code to support bit offsets of more than 8 bits. Signed-off-by: Dmitry Baryshkov --- drivers/nvmem/core.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index d6494dfc20a7324bde6415776dcabbb0bfdd334b..7fa85b0804db360035d7471002dbf79658d5830b 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -834,7 +834,9 @@ static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_nod if (addr && len == (2 * sizeof(u32))) { info.bit_offset = be32_to_cpup(addr++); info.nbits = be32_to_cpup(addr); - if (info.bit_offset >= BITS_PER_BYTE || info.nbits < 1) { + if (info.bit_offset >= BITS_PER_BYTE * info.bytes || + info.nbits < 1 || + info.bit_offset + info.nbits > BITS_PER_BYTE * info.bytes) { dev_err(dev, "nvmem: invalid bits on %pOF\n", child); of_node_put(child); return -EINVAL; @@ -1627,21 +1629,29 @@ EXPORT_SYMBOL_GPL(nvmem_cell_put); static void nvmem_shift_read_buffer_in_place(struct nvmem_cell_entry *cell, void *buf) { u8 *p, *b; - int i, extra, bit_offset = cell->bit_offset; + int i, extra, bytes_offset; + int bit_offset = cell->bit_offset; p = b = buf; - if (bit_offset) { + + bytes_offset = bit_offset / BITS_PER_BYTE; + b += bytes_offset; + bit_offset %= BITS_PER_BYTE; + + if (bit_offset % BITS_PER_BYTE) { /* First shift */ - *b++ >>= bit_offset; + *p = *b++ >> bit_offset; /* setup rest of the bytes if any */ for (i = 1; i < cell->bytes; i++) { /* Get bits from next byte and shift them towards msb */ - *p |= *b << (BITS_PER_BYTE - bit_offset); + *p++ |= *b << (BITS_PER_BYTE - bit_offset); - p = b; - *b++ >>= bit_offset; + *p = *b++ >> bit_offset; } + } else if (p != b) { + memmove(p, b, cell->bytes - bytes_offset); + p += cell->bytes - 1; } else { /* point to the msb */ p += cell->bytes - 1;