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Wed, 8 Jan 2025 22:43:05 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 14:43:00 -0800 From: Akhil P Oommen Date: Thu, 9 Jan 2025 04:12:38 +0530 Subject: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250109-x1e-speedbin-b4-v1-1-009e812b7f2a@quicinc.com> References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> In-Reply-To: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla CC: , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; 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Add support for this new "hi" bit along with the speedbin mappings. --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { .gmu_cgc_mode = 0x00020202, }, .address_space_size = SZ_256G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 263, 1 }, + { 315, 0 }, + ), .preempt_record_size = 4192 * SZ_1K, }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) int adreno_read_speedbin(struct device *dev, u32 *speedbin) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 hi_bits = 0; + int ret; + + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + if (ret) + return ret; + + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); + if (ret != -ENOENT) + return ret; + + *speedbin |= (hi_bits << 8); + return 0; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,