| Message ID | 20250125-topic-x1p4_dts-v1-4-02659a08b044@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | X1P42100 DT and PCIe PHY bits | expand |
On Sat, Jan 25, 2025 at 04:31:20AM +0100, Konrad Dybcio wrote: > From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > Asserting the NOCSR reset line keeps the PHY registers in tact. > This allows us to avoid programming long tables of magic values in the > operating system. > > Wire up these resets to PCIe PHY4 and 5 (it's there on the others). > > Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9d38436763432892ceef95daf0335d4cf446357c..a244cbb84aecc23ce11414c41f2e5d0905f455ee 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3558,8 +3558,10 @@ pcie5_phy: phy@1c06000 { "pipe", "pipediv2"; - resets = <&gcc GCC_PCIE_5_PHY_BCR>; - reset-names = "phy"; + resets = <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -3692,8 +3694,10 @@ pcie4_phy: phy@1c0e000 { "pipe", "pipediv2"; - resets = <&gcc GCC_PCIE_4_PHY_BCR>; - reset-names = "phy"; + resets = <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>;