@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
@@ -983,8 +984,8 @@ mmcc: clock-controller@fd8c0000 {
<&gcc GPLL0_VOTE>,
<&gcc GPLL1_VOTE>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
- <&mdss_dsi0_phy 1>,
- <&mdss_dsi0_phy 0>;
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>;
clock-names = "xo",
"mmss_gpll0_vote",
"gpll0_vote",
@@ -1060,8 +1061,8 @@ mdss_dsi0: dsi@fd922800 {
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi0_phy 0>,
- <&mdss_dsi0_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Depends on: https://lore.kernel.org/all/20250127132105.107138-1-krzysztof.kozlowski@linaro.org/ Please wait with merging till this hit mainline. --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)