@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8917.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -961,8 +962,8 @@ gcc: clock-controller@1800000 {
#power-domain-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
- <&mdss_dsi0_phy 1>,
- <&mdss_dsi0_phy 0>;
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>;
clock-names = "xo",
"sleep_clk",
"dsi0pll",
@@ -1051,8 +1052,8 @@ mdss_dsi0: dsi@1a94000 {
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi0_phy 0>,
- <&mdss_dsi0_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Depends on: https://lore.kernel.org/all/20250127132105.107138-1-krzysztof.kozlowski@linaro.org/ Please wait with merging till this hit mainline. --- arch/arm64/boot/dts/qcom/msm8917.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)