| Message ID | 20250128062708.573662-6-quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe support for Qualcomm IPQ5332 | expand |
On Tue, Jan 28, 2025 at 11:57:06AM +0530, Varadarajan Narayanan wrote: > Document the PCIe controller on IPQ5332 platform. IPQ5332 will > use IPQ9574 as the fall back compatible. > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v9: Remove superfluous ipq5332 constraint since the fallback is present > > v8: Use ipq9574 as fallback compatible for ipq5332 along with ipq5424 > > v7: Moved ipq9574 related changes to a separate patch > Add 'global' interrupt > > v6: Commit message update only. Add info regarding the moving of > ipq9574 from 5 "reg" definition to 5 or 6 reg definition. > > v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts > > v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332 > * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able > to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check > and dt_binding_check flag errors. > --- Same problems as ipq5424. What's more, you are doing the same, so this is a conflicting change coming from the same company or even the same team. It is not the open source community's job, not the maintainer's job to coordinate tasks and teams in Qualcomm. Qualcomm people should coordinate their teams. It's merge window, you and your colleagues keep sending new versions of big patchsets with conflicting changes, without any coordination. Amount of patches is just overwhelming. Lack of coordination and any reflection is just discouraging. Can you slow down and actually sync to send something reasonable? And not during the merge window? Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 4b4927178abc..f7ea865f56bc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -33,6 +33,7 @@ properties: - qcom,pcie-sdx55 - items: - enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 - const: qcom,pcie-ipq9574 - items: @@ -49,11 +50,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 @@ -443,6 +444,7 @@ allOf: interrupts: minItems: 8 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -452,6 +454,7 @@ allOf: - const: msi5 - const: msi6 - const: msi7 + - const: global - if: properties: @@ -559,6 +562,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074
Document the PCIe controller on IPQ5332 platform. IPQ5332 will use IPQ9574 as the fall back compatible. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- v9: Remove superfluous ipq5332 constraint since the fallback is present v8: Use ipq9574 as fallback compatible for ipq5332 along with ipq5424 v7: Moved ipq9574 related changes to a separate patch Add 'global' interrupt v6: Commit message update only. Add info regarding the moving of ipq9574 from 5 "reg" definition to 5 or 6 reg definition. v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332 * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check and dt_binding_check flag errors. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)