Message ID | 20250203-topic-x1p4_dts-v2-2-72cd4cdc767b@oss.qualcomm.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
Series | X1P42100 DT and PCIe PHY bits | expand |
On Mon, Feb 03, 2025 at 03:43:21PM +0100, Konrad Dybcio wrote: > From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > (Almost?) all QMP PHYs come with both a "full reset" ("phy") and a > "retain certain registers" one ("phy_nocsr"). > > Drop the maxItems=1 constraint for resets and reset_names as we go > ahead and straighten out the DT usage. After that's done (which > will involve modifying some clock drivers etc.), we may set > *min*Items to 2, bar some possible exceptions. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 ------ > 1 file changed, 6 deletions(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 51eaffa45c18df15f93f7a3c7382415a59982793..af8c4aa4f43dfb8268c31d64ccdd5c4be7a4def5 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -220,12 +220,6 @@ allOf: minItems: 2 reset-names: minItems: 2 - else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 - if: properties: