@@ -20,6 +20,7 @@
#define MHI_TIMEOUT_DEFAULT_MS 20000
#define RDDM_DUMP_SIZE 0x420000
#define MHI_CB_INVALID 0xff
+#define MHI_BW_SCALE_CHAN_DB 126
static const struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
{
@@ -73,6 +74,17 @@ static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
.client_managed = false,
.offload_channel = false,
},
+ {
+ .num_elements = 8,
+ .irq_moderation_ms = 0,
+ .irq = 1,
+ .mode = MHI_DB_BRST_DISABLE,
+ .data_type = MHI_ER_BW_SCALE,
+ .priority = 2,
+ .hardware_event = false,
+ .client_managed = false,
+ .offload_channel = false,
+ },
};
static const struct mhi_controller_config ath11k_mhi_config_qca6390 = {
@@ -313,6 +325,33 @@ static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
writel(val, addr);
}
+static int ath11k_mhi_op_get_misc_doorbell(struct mhi_controller *mhi_cntrl,
+ enum mhi_er_data_type type)
+{
+ if (type == MHI_ER_BW_SCALE)
+ return MHI_BW_SCALE_CHAN_DB;
+
+ return -EINVAL;
+}
+
+static int ath11k_mhi_op_bw_scale(struct mhi_controller *mhi_cntrl,
+ struct mhi_link_info *link_info)
+{
+ struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
+ struct pci_dev *pci_dev = to_pci_dev(ab->dev);
+ struct pci_dev *pdev;
+ u8 speed = pcie_link_speed[link_info->target_link_speed];
+
+ if (!pci_dev)
+ return -EINVAL;
+
+ pdev = pci_upstream_bridge(pci_dev);
+ if (!pdev)
+ return -ENODEV;
+
+ return pcie_set_target_speed(pdev, speed, true);
+}
+
static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
{
struct device_node *np;
@@ -389,6 +428,8 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
+ mhi_ctrl->bw_scale = ath11k_mhi_op_bw_scale;
+ mhi_ctrl->get_misc_doorbell = ath11k_mhi_op_get_misc_doorbell;
switch (ab->hw_rev) {
case ATH11K_HW_QCN9074_HW10: