| Message ID | 20250217-sar2130p-pci-v1-2-94b20ec70a14@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On Mon, Feb 17, 2025 at 08:56:14PM +0200, Dmitry Baryshkov wrote: > Qualcomm SM8450 platform can (and should) be using DMA for the PCIe EP > transfers. Extend the MMIO regions and interrupts in order to acommodate > for the DMA resources. Upstream DT doesn't provide support for the EP > mode of the PCIe controller, so while this is an ABI break, it doesn't > break any of the supported platforms. > > Fixes: 63e445b746aa ("dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 800accdf5947e7178ad80f0759cf53111be1a814..460191fc4ff1b64206bce89e15ce38e59c112ba6 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -173,9 +173,9 @@ allOf: > then: > properties: > reg: > - maxItems: 6 > + maxItems: 7 > reg-names: > - maxItems: 6 > + maxItems: 7 > clocks: > items: > - description: PCIe Auxiliary clock > @@ -197,9 +197,9 @@ allOf: > - const: ddrss_sf_tbu > - const: aggre_noc_axi > interrupts: > - maxItems: 2 > + maxItems: 3 > interrupt-names: > - maxItems: 2 > + maxItems: 3 > > - if: > properties: > > -- > 2.39.5 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 800accdf5947e7178ad80f0759cf53111be1a814..460191fc4ff1b64206bce89e15ce38e59c112ba6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -173,9 +173,9 @@ allOf: then: properties: reg: - maxItems: 6 + maxItems: 7 reg-names: - maxItems: 6 + maxItems: 7 clocks: items: - description: PCIe Auxiliary clock @@ -197,9 +197,9 @@ allOf: - const: ddrss_sf_tbu - const: aggre_noc_axi interrupts: - maxItems: 2 + maxItems: 3 interrupt-names: - maxItems: 2 + maxItems: 3 - if: properties:
Qualcomm SM8450 platform can (and should) be using DMA for the PCIe EP transfers. Extend the MMIO regions and interrupts in order to acommodate for the DMA resources. Upstream DT doesn't provide support for the EP mode of the PCIe controller, so while this is an ABI break, it doesn't break any of the supported platforms. Fixes: 63e445b746aa ("dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)