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[2001:14ba:a0c3:3a00::782]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5462006b0ecsm559806e87.160.2025.02.17.10.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 10:56:22 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 17 Feb 2025 20:56:14 +0200 Subject: [PATCH 2/6] dt-bindings: PCI: qcom-ep: enable DMA for SM8450 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250217-sar2130p-pci-v1-2-94b20ec70a14@linaro.org> References: <20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org> In-Reply-To: <20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1524; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=l4JKzQ7pT7dVKATcLHSyA8F/AwMI6R5uxNc1u1FYr2M=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBns4ZPWq89hJ26Q/eFUKUe1IK+q3E5JsH6r76PA 2E+VX3413+JAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZ7OGTwAKCRAU23LtvoBl uOhHEAC2NdE9o/AGIi7osGKgLOcKSpXu1swFXSoUf2bzkz3MuEImLUcfqu0tE6eRU6ljFDsBq1+ ML86ZgpBM6Aev9ZUVEM119lGLwb0S3xWNVOmx6N7DOnf23viSZ+txgggjd7F4wg6MClkdfrEK0G f6sIOgMLYx/g7T5oNXdrUxjPee1qW1Jjq6xb4F9N2LM3uGJKxNTUAp0vjAasJcSw8gIv2iedGEK 2XWly4PX7Kdxd/mYhmQTcQKMUz8JJnoNtCktjxZhRHLFeNqNkYG+3faKxt9DgOgacwE43QEyoSE ieh/MHGmU0T6xwzr6jus4bM/sjQcHWdz3QLbyHo2wZTDvwAfCpy9tXRXMFVy+UHUqR6iFpVqGvM YQT5ZfuKqeNj6D/kmzOmzSK6oz7isEB0FrpeaehmDcJyry4+5vQO+kDoy84P7ZLRlCSdwdH6qb2 /ZogTYfFE6PxN5JhRsUmcTjDD8G1SX8JckKo/yEeXtsiuiPNpB5ZL5jMcc3+nG5YXaYCC7irCfp O3NEpH57Sr3z8PdvL5NieSXpapmgtZUJXbLmIyj/OqB8TxI/cNzTVfLNNRsd6FCe0kdfVszPR88 qeQWMtdT50en+Q1+y8G1fBLxZXdVPHnlKRnzOxehfX6axmqdM6nIzRWO8MB6/M0yILPmB/VephT aOULzSgydXDrqwA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Qualcomm SM8450 platform can (and should) be using DMA for the PCIe EP transfers. Extend the MMIO regions and interrupts in order to acommodate for the DMA resources. Upstream DT doesn't provide support for the EP mode of the PCIe controller, so while this is an ABI break, it doesn't break any of the supported platforms. Fixes: 63e445b746aa ("dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC") Signed-off-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 800accdf5947e7178ad80f0759cf53111be1a814..460191fc4ff1b64206bce89e15ce38e59c112ba6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -173,9 +173,9 @@ allOf: then: properties: reg: - maxItems: 6 + maxItems: 7 reg-names: - maxItems: 6 + maxItems: 7 clocks: items: - description: PCIe Auxiliary clock @@ -197,9 +197,9 @@ allOf: - const: ddrss_sf_tbu - const: aggre_noc_axi interrupts: - maxItems: 2 + maxItems: 3 interrupt-names: - maxItems: 2 + maxItems: 3 - if: properties: