| Message ID | 20250217-sar2130p-pci-v1-3-94b20ec70a14@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On Mon, Feb 17, 2025 at 08:56:15PM +0200, Dmitry Baryshkov wrote: > Add support for using the PCI controller in the endpoint mode on the > SAR2130P platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 44 +++++++++++++++++++++- > 1 file changed, 42 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 460191fc4ff1b64206bce89e15ce38e59c112ba6..6e516589f0edb4dfec78f9ff5493c06ee25418f0 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -14,6 +14,7 @@ properties: > oneOf: > - enum: > - qcom,sa8775p-pcie-ep > + - qcom,sar2130p-pcie-ep > - qcom,sdx55-pcie-ep > - qcom,sm8450-pcie-ep > - items: > @@ -44,11 +45,11 @@ properties: > > clocks: > minItems: 5 > - maxItems: 8 > + maxItems: 9 > > clock-names: > minItems: 5 > - maxItems: 8 > + maxItems: 9 > > qcom,perst-regs: > description: Reference to a syscon representing TCSR followed by the two > @@ -129,6 +130,45 @@ required: > > allOf: > - $ref: pci-ep.yaml# > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sar2130p-pcie-ep > + then: > + properties: > + reg: > + maxItems: 7 > + reg-names: > + maxItems: 7 > + clocks: > + items: > + - description: PCIe Auxiliary clock > + - description: PCIe CFG AHB clock > + - description: PCIe Master AXI clock > + - description: PCIe Slave AXI clock > + - description: PCIe Slave Q2A AXI clock > + - description: PCIe DDRSS SF TBU clock > + - description: PCIe AGGRE NOC AXI clock > + - description: PCIe CFG NOC AXI clock > + - description: PCIe QMIP AHB clock > + clock-names: > + items: > + - const: aux > + - const: cfg > + - const: bus_master > + - const: bus_slave > + - const: slave_q2a > + - const: ddrss_sf_tbu > + - const: aggre_noc_axi > + - const: cnoc_sf_axi > + - const: qmip_pcie_ahb > + interrupts: > + maxItems: 3 > + interrupt-names: > + maxItems: 3 > + > - if: > properties: > compatible: > > -- > 2.39.5 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 460191fc4ff1b64206bce89e15ce38e59c112ba6..6e516589f0edb4dfec78f9ff5493c06ee25418f0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sa8775p-pcie-ep + - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -44,11 +45,11 @@ properties: clocks: minItems: 5 - maxItems: 8 + maxItems: 9 clock-names: minItems: 5 - maxItems: 8 + maxItems: 9 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -129,6 +130,45 @@ required: allOf: - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sar2130p-pcie-ep + then: + properties: + reg: + maxItems: 7 + reg-names: + maxItems: 7 + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + - description: PCIe CFG NOC AXI clock + - description: PCIe QMIP AHB clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ddrss_sf_tbu + - const: aggre_noc_axi + - const: cnoc_sf_axi + - const: qmip_pcie_ahb + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 + - if: properties: compatible:
Add support for using the PCI controller in the endpoint mode on the SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 44 +++++++++++++++++++++- 1 file changed, 42 insertions(+), 2 deletions(-)