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Wed, 19 Feb 2025 19:49:57 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Feb 2025 11:49:57 -0800 From: Jessica Zhang Date: Wed, 19 Feb 2025 11:49:18 -0800 Subject: [PATCH v3 2/5] drm/msm/iommu: rename msm_fault_handler to msm_gpu_fault_handler Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250219-abhinavk-smmu-fault-handler-v3-2-aa3f0bf4434a@quicinc.com> References: <20250219-abhinavk-smmu-fault-handler-v3-0-aa3f0bf4434a@quicinc.com> In-Reply-To: <20250219-abhinavk-smmu-fault-handler-v3-0-aa3f0bf4434a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" CC: Abhinav Kumar , , , , , "Jessica Zhang" X-Mailer: b4 0.15-dev-f0f05 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739994597; l=1774; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=vgPDXDqUxj8n/dCQlEEd8aA5R+3YKMV0KJToIhdliOM=; b=V/I0ku8UIXSIpL1MJQpXQtdSzFfVGXZjklgPzgaXvPrWHOKFCBrSpM1vD/xoturrOpb0Xgzob nLfXXb05A3hA44rsvroRwVIDh43M+4H6cZN7bz3w2qJb/M2JqbMqnhQ X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PqccdSaxqhwEYLY2R1JMzN3YA8CTPpOT X-Proofpoint-ORIG-GUID: PqccdSaxqhwEYLY2R1JMzN3YA8CTPpOT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-19_08,2025-02-19_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=785 spamscore=0 adultscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502190153 From: Abhinav Kumar In preparation of registering a separate fault handler for display, lets rename the existing msm_fault_handler to msm_gpu_fault_handler. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/msm_iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 2a94e82316f9..20518bf9898a 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -243,7 +243,7 @@ static const struct iommu_flush_ops tlb_ops = { .tlb_add_page = msm_iommu_tlb_add_page, }; -static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, +static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg); struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) @@ -319,7 +319,7 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) return &pagetable->base; } -static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, +static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { struct msm_iommu *iommu = arg; @@ -448,7 +448,7 @@ struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsig return mmu; iommu = to_msm_iommu(mmu); - iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); + iommu_set_fault_handler(iommu->domain, msm_gpu_fault_handler, iommu); /* Enable stall on iommu fault: */ if (adreno_smmu->set_stall)