Message ID | 20250221-sar2130p-pci-v3-2-61a0fdfb75b4@linaro.org (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On Fri, Feb 21, 2025 at 05:52:00PM +0200, Dmitry Baryshkov wrote: > Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and > DDR. For example, SA8775P specifies the iommu alththough it is not a > part of bindings. Change the schema in order to require the IOMMU for > SA8775P and forbid it from being used on SDX55 (SM8450 will be handled > in a later patch). > > This fixes the following warning: > > pcie-ep@1c10000: Unevaluated properties are not allowed ('iommus' was unexpected) > > Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Feb 21, 2025 at 05:52:00PM +0200, Dmitry Baryshkov wrote: > Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and > DDR. For example, SA8775P specifies the iommu alththough it is not a > part of bindings. Change the schema in order to require the IOMMU for > SA8775P and forbid it from being used on SDX55 (SM8450 will be handled > in a later patch). > > This fixes the following warning: > > pcie-ep@1c10000: Unevaluated properties are not allowed ('iommus' was unexpected) > > Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 0c2ca4cfa3b190b3fb204f0d7142370734fb3534..6075361348352bb8d607acecc76189e28b03dc5b 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -75,6 +75,9 @@ properties: > - const: doorbell > - const: dma > > + iommus: > + maxItems: 1 > + > reset-gpios: > description: GPIO used as PERST# input signal > maxItems: 1 > @@ -162,6 +165,7 @@ allOf: > maxItems: 2 > interrupt-names: > maxItems: 2 > + iommus: false > > - if: > properties: > @@ -234,6 +238,8 @@ allOf: > interrupt-names: > minItems: 3 > maxItems: 3 > + required: > + - iommus > > unevaluatedProperties: false > > > -- > 2.39.5 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 0c2ca4cfa3b190b3fb204f0d7142370734fb3534..6075361348352bb8d607acecc76189e28b03dc5b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -75,6 +75,9 @@ properties: - const: doorbell - const: dma + iommus: + maxItems: 1 + reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 @@ -162,6 +165,7 @@ allOf: maxItems: 2 interrupt-names: maxItems: 2 + iommus: false - if: properties: @@ -234,6 +238,8 @@ allOf: interrupt-names: minItems: 3 maxItems: 3 + required: + - iommus unevaluatedProperties: false
Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and DDR. For example, SA8775P specifies the iommu alththough it is not a part of bindings. Change the schema in order to require the IOMMU for SA8775P and forbid it from being used on SDX55 (SM8450 will be handled in a later patch). This fixes the following warning: pcie-ep@1c10000: Unevaluated properties are not allowed ('iommus' was unexpected) Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 6 ++++++ 1 file changed, 6 insertions(+)