| Message ID | 20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-12-eb5df105c807@linaro.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | drm/msm/dpu: Support quad pipe with dual-DSI | expand |
On 3/3/2025 7:14 AM, Jun Nie wrote: > Currently, only 2 pipes are used at most for a plane. A stage structure > describes the configuration for a mixer pair. So only one stage is needed > for current usage cases. The quad-pipe case will be added in future and 2 > stages are used in the case. So extend the stage to an array with array > size STAGES_PER_PLANE and blend pipes per mixer pair with configuration > in the stage structure. > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 46 +++++++++++++++++++++----------- > 1 file changed, 30 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index 81474823e6799132db71c9712046d359e3535d90..6fbe42e8988edac7e7917ae8de180aefdaf443e9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -392,7 +392,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) > static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, > struct drm_plane *plane, > struct dpu_crtc_mixer *mixer, > - u32 num_mixers, > + u32 lms_in_stage, > enum dpu_stage stage, > const struct msm_format *format, > uint64_t modifier, > @@ -426,7 +426,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, > stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; > > /* blend config update */ > - for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) > + for (lm_idx = 0; lm_idx < lms_in_stage; lm_idx++) > mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); > } > > @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, > const struct msm_format *format; > struct dpu_hw_ctl *ctl = mixer->lm_ctl; > > - uint32_t lm_idx, i; > + uint32_t lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_stage; > bool bg_alpha_enable = false; > DECLARE_BITMAP(fetch_active, SSPP_MAX); > > @@ -463,15 +463,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, > if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) > bg_alpha_enable = true; > > - for (i = 0; i < PIPES_PER_PLANE; i++) { > - if (!pstate->pipe[i].sspp) > - continue; > - set_bit(pstate->pipe[i].sspp->idx, fetch_active); > - _dpu_crtc_blend_setup_pipe(crtc, plane, > - mixer, cstate->num_mixers, > - pstate->stage, > - format, fb ? fb->modifier : 0, > - &pstate->pipe[i], i, stage_cfg); > + /* loop pipe per mixer pair with config in stage structure */ > + for (stage = 0; stage < STAGES_PER_PLANE; stage++) { > + head_pipe_in_stage = stage * PIPES_PER_STAGE; > + for (i = 0; i < PIPES_PER_STAGE; i++) { > + pipe_idx = i + head_pipe_in_stage; > + if (!pstate->pipe[pipe_idx].sspp) > + continue; > + > + lms_in_stage = min(cstate->num_mixers - (stage * PIPES_PER_STAGE), > + PIPES_PER_STAGE); > + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active); > + _dpu_crtc_blend_setup_pipe(crtc, plane, > + &mixer[head_pipe_in_stage], > + lms_in_stage, > + pstate->stage, > + format, fb ? fb->modifier : 0, > + &pstate->pipe[pipe_idx], i, > + &stage_cfg[stage]); > + } > } > > /* blend config update */ > @@ -503,7 +513,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) > struct dpu_crtc_mixer *mixer = cstate->mixers; > struct dpu_hw_ctl *ctl; > struct dpu_hw_mixer *lm; > - struct dpu_hw_stage_cfg stage_cfg; > + struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE]; > int i; > > DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); > @@ -516,9 +526,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) > } > > /* initialize stage cfg */ > - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); > + memset(&stage_cfg, 0, sizeof(stage_cfg)); > > - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); > + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg); > > for (i = 0; i < cstate->num_mixers; i++) { > ctl = mixer[i].lm_ctl; > @@ -535,8 +545,12 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) > mixer[i].mixer_op_mode, > ctl->idx - CTL_0); > > + /* > + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. > + * stage data is shared between PIPES_PER_STAGE pipes. > + */ > ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, > - &stage_cfg); > + &stage_cfg[i / PIPES_PER_STAGE]); > } > } > > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 81474823e6799132db71c9712046d359e3535d90..6fbe42e8988edac7e7917ae8de180aefdaf443e9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -392,7 +392,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, struct drm_plane *plane, struct dpu_crtc_mixer *mixer, - u32 num_mixers, + u32 lms_in_stage, enum dpu_stage stage, const struct msm_format *format, uint64_t modifier, @@ -426,7 +426,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; /* blend config update */ - for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) + for (lm_idx = 0; lm_idx < lms_in_stage; lm_idx++) mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); } @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t lm_idx, i; + uint32_t lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_stage; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); @@ -463,15 +463,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - for (i = 0; i < PIPES_PER_PLANE; i++) { - if (!pstate->pipe[i].sspp) - continue; - set_bit(pstate->pipe[i].sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe[i], i, stage_cfg); + /* loop pipe per mixer pair with config in stage structure */ + for (stage = 0; stage < STAGES_PER_PLANE; stage++) { + head_pipe_in_stage = stage * PIPES_PER_STAGE; + for (i = 0; i < PIPES_PER_STAGE; i++) { + pipe_idx = i + head_pipe_in_stage; + if (!pstate->pipe[pipe_idx].sspp) + continue; + + lms_in_stage = min(cstate->num_mixers - (stage * PIPES_PER_STAGE), + PIPES_PER_STAGE); + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + &mixer[head_pipe_in_stage], + lms_in_stage, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe[pipe_idx], i, + &stage_cfg[stage]); + } } /* blend config update */ @@ -503,7 +513,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer = cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; - struct dpu_hw_stage_cfg stage_cfg; + struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE]; int i; DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -516,9 +526,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } /* initialize stage cfg */ - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(stage_cfg)); - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg); for (i = 0; i < cstate->num_mixers; i++) { ctl = mixer[i].lm_ctl; @@ -535,8 +545,12 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) mixer[i].mixer_op_mode, ctl->idx - CTL_0); + /* + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. + * stage data is shared between PIPES_PER_STAGE pipes. + */ ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + &stage_cfg[i / PIPES_PER_STAGE]); } }