| Message ID | 20250327-videocc-pll-multi-pd-voting-v3-1-895fafd62627@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On Thu, Mar 27, 2025 at 03:22:21PM +0530, Jagadeesh Kona wrote: > To configure the video PLLs and enable the video GDSCs on SM8450, > SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along Either your patches are not ordered correctly or you forgot that SC8280xp also gets MXC. Best regards, Krzysztof
On Fri, Mar 28, 2025 at 09:09:00AM +0100, Krzysztof Kozlowski wrote: > On Thu, Mar 27, 2025 at 03:22:21PM +0530, Jagadeesh Kona wrote: > > To configure the video PLLs and enable the video GDSCs on SM8450, > > SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along > > Either your patches are not ordered correctly or you forgot that > SC8280xp also gets MXC. Ah, no, that's videocc, I mixed up devices. It's fine. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 62714fa54db82491a7a108f7f18a253d737f8d61..93807b1448025a4f2724378346a4bd87f08a8e57 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,14 +32,18 @@ properties: - description: Video AHB clock from GCC power-domains: - maxItems: 1 description: - MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + Phandles to OPP nodes that describe required performance point on power domains + items: + - description: MMCX performance point + - description: MXC performance point required: - compatible @@ -72,8 +76,10 @@ examples: reg = <0x0aaf0000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
To configure the video PLLs and enable the video GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the videocc bindings to include the MXC power domain on these platforms. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-)