| Message ID | 20250327-videocc-pll-multi-pd-voting-v3-12-895fafd62627@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On 27/03/2025 09:52, Jagadeesh Kona wrote: > Camera PLLs on X1E80100 require both MMCX and MXC rails to be kept ON > to configure the PLLs properly. Hence move runtime power management, > PLL configuration and enabling critical clocks to qcom_cc_really_probe() > which ensures all required power domains are in enabled state before > configuring the PLLs or enabling the clocks. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- > drivers/clk/qcom/camcc-x1e80100.c | 63 +++++++++++++++++---------------------- > 1 file changed, 28 insertions(+), 35 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c > index b73524ae64b1b2b1ee94ceca88b5f3b46143f20b..1f2e49c4798f33b2204b95665cc977b4a52b549a 100644 > --- a/drivers/clk/qcom/camcc-x1e80100.c > +++ b/drivers/clk/qcom/camcc-x1e80100.c > @@ -7,7 +7,6 @@ > #include <linux/mod_devicetable.h> > #include <linux/module.h> > #include <linux/platform_device.h> > -#include <linux/pm_runtime.h> > #include <linux/regmap.h> > > #include <dt-bindings/clock/qcom,x1e80100-camcc.h> > @@ -67,6 +66,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { > > static struct clk_alpha_pll cam_cc_pll0 = { > .offset = 0x0, > + .config = &cam_cc_pll0_config, > .vco_table = lucid_ole_vco, > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -144,6 +144,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { > > static struct clk_alpha_pll cam_cc_pll1 = { > .offset = 0x1000, > + .config = &cam_cc_pll1_config, > .vco_table = lucid_ole_vco, > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -194,6 +195,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = { > > static struct clk_alpha_pll cam_cc_pll2 = { > .offset = 0x2000, > + .config = &cam_cc_pll2_config, > .vco_table = rivian_ole_vco, > .num_vco = ARRAY_SIZE(rivian_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], > @@ -225,6 +227,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { > > static struct clk_alpha_pll cam_cc_pll3 = { > .offset = 0x3000, > + .config = &cam_cc_pll3_config, > .vco_table = lucid_ole_vco, > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -279,6 +282,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { > > static struct clk_alpha_pll cam_cc_pll4 = { > .offset = 0x4000, > + .config = &cam_cc_pll4_config, > .vco_table = lucid_ole_vco, > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -333,6 +337,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = { > > static struct clk_alpha_pll cam_cc_pll6 = { > .offset = 0x6000, > + .config = &cam_cc_pll6_config, > .vco_table = lucid_ole_vco, > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -387,6 +392,7 @@ static const struct alpha_pll_config cam_cc_pll8_config = { > > static struct clk_alpha_pll cam_cc_pll8 = { > .offset = 0x8000, > + .config = &cam_cc_pll8_config, > .vco_table = lucid_ole_vco, > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -2418,6 +2424,21 @@ static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { > [CAM_CC_SFE_0_BCR] = { 0x1327c }, > }; > > +static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = { > + &cam_cc_pll0, > + &cam_cc_pll1, > + &cam_cc_pll2, > + &cam_cc_pll3, > + &cam_cc_pll4, > + &cam_cc_pll6, > + &cam_cc_pll8, > +}; > + > +static u32 cam_cc_x1e80100_critical_cbcrs[] = { > + 0x13a9c, /* CAM_CC_GDSC_CLK */ > + 0x13ab8, /* CAM_CC_SLEEP_CLK */ > +}; > + > static const struct regmap_config cam_cc_x1e80100_regmap_config = { > .reg_bits = 32, > .reg_stride = 4, > @@ -2434,6 +2455,11 @@ static const struct qcom_cc_desc cam_cc_x1e80100_desc = { > .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), > .gdscs = cam_cc_x1e80100_gdscs, > .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), > + .alpha_plls = cam_cc_x1e80100_plls, > + .num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls), > + .clk_cbcrs = cam_cc_x1e80100_critical_cbcrs, > + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1e80100_critical_cbcrs), > + .use_rpm = true, > }; > > static const struct of_device_id cam_cc_x1e80100_match_table[] = { > @@ -2444,40 +2470,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); > > static int cam_cc_x1e80100_probe(struct platform_device *pdev) > { > - struct regmap *regmap; > - int ret; > - > - ret = devm_pm_runtime_enable(&pdev->dev); > - if (ret) > - return ret; > - > - ret = pm_runtime_resume_and_get(&pdev->dev); > - if (ret) > - return ret; > - > - regmap = qcom_cc_map(pdev, &cam_cc_x1e80100_desc); > - if (IS_ERR(regmap)) { > - pm_runtime_put(&pdev->dev); > - return PTR_ERR(regmap); > - } > - > - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); > - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); > - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); > - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); > - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); > - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); > - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); > - > - /* Keep clocks always enabled */ > - qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ > - qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ > - > - ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_x1e80100_desc, regmap); > - > - pm_runtime_put(&pdev->dev); > - > - return ret; > + return qcom_cc_probe(pdev, &cam_cc_x1e80100_desc); > } > > static struct platform_driver cam_cc_x1e80100_driver = { > Thanks for this work. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # Dell Inspiron 14 Plus 7441
diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c index b73524ae64b1b2b1ee94ceca88b5f3b46143f20b..1f2e49c4798f33b2204b95665cc977b4a52b549a 100644 --- a/drivers/clk/qcom/camcc-x1e80100.c +++ b/drivers/clk/qcom/camcc-x1e80100.c @@ -7,7 +7,6 @@ #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> -#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,x1e80100-camcc.h> @@ -67,6 +66,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { static struct clk_alpha_pll cam_cc_pll0 = { .offset = 0x0, + .config = &cam_cc_pll0_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -144,6 +144,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { static struct clk_alpha_pll cam_cc_pll1 = { .offset = 0x1000, + .config = &cam_cc_pll1_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -194,6 +195,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = { static struct clk_alpha_pll cam_cc_pll2 = { .offset = 0x2000, + .config = &cam_cc_pll2_config, .vco_table = rivian_ole_vco, .num_vco = ARRAY_SIZE(rivian_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -225,6 +227,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { static struct clk_alpha_pll cam_cc_pll3 = { .offset = 0x3000, + .config = &cam_cc_pll3_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -279,6 +282,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { static struct clk_alpha_pll cam_cc_pll4 = { .offset = 0x4000, + .config = &cam_cc_pll4_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -333,6 +337,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = { static struct clk_alpha_pll cam_cc_pll6 = { .offset = 0x6000, + .config = &cam_cc_pll6_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -387,6 +392,7 @@ static const struct alpha_pll_config cam_cc_pll8_config = { static struct clk_alpha_pll cam_cc_pll8 = { .offset = 0x8000, + .config = &cam_cc_pll8_config, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -2418,6 +2424,21 @@ static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { [CAM_CC_SFE_0_BCR] = { 0x1327c }, }; +static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll6, + &cam_cc_pll8, +}; + +static u32 cam_cc_x1e80100_critical_cbcrs[] = { + 0x13a9c, /* CAM_CC_GDSC_CLK */ + 0x13ab8, /* CAM_CC_SLEEP_CLK */ +}; + static const struct regmap_config cam_cc_x1e80100_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -2434,6 +2455,11 @@ static const struct qcom_cc_desc cam_cc_x1e80100_desc = { .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), .gdscs = cam_cc_x1e80100_gdscs, .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), + .alpha_plls = cam_cc_x1e80100_plls, + .num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls), + .clk_cbcrs = cam_cc_x1e80100_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1e80100_critical_cbcrs), + .use_rpm = true, }; static const struct of_device_id cam_cc_x1e80100_match_table[] = { @@ -2444,40 +2470,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); static int cam_cc_x1e80100_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret = devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret = pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap = qcom_cc_map(pdev, &cam_cc_x1e80100_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); - - /* Keep clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ - - ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_x1e80100_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; + return qcom_cc_probe(pdev, &cam_cc_x1e80100_desc); } static struct platform_driver cam_cc_x1e80100_driver = {
Camera PLLs on X1E80100 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enabling critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- drivers/clk/qcom/camcc-x1e80100.c | 63 +++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 35 deletions(-)