| Message ID | 20250327-videocc-pll-multi-pd-voting-v3-3-895fafd62627@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On 27/03/2025 09:52, Jagadeesh Kona wrote: > - A phandle to an OPP node describing required MMCX performance point. > + Phandles to OPP nodes that describe required performance point on power domains I believe we are dropping "Phandle to" generally as this is a redundant statement. You should also pluralise performance-points. .. required performance-points on power-domains Other than that Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- bod
On Thu, Mar 27, 2025 at 03:22:23PM +0530, Jagadeesh Kona wrote: > From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > > To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475, > SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. > Therefore, update the camcc bindings to include the MXC power domain on > these platforms. > > Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock controller") > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- > .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 3/27/2025 8:58 PM, Bryan O'Donoghue wrote: > On 27/03/2025 09:52, Jagadeesh Kona wrote: >> - A phandle to an OPP node describing required MMCX performance point. >> + Phandles to OPP nodes that describe required performance point on power domains > > I believe we are dropping "Phandle to" generally as this is a redundant statement. > > You should also pluralise performance-points. > > .. required performance-points on power-domains > > Other than that > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Yes, I will fix above in the next series. Thanks, Jagadeesh > --- > bod
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 883f12e3d11fa16384108434f6de120162226a28..927258cad89d93c7f6ce60c3fda53d094081c063 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -35,14 +35,18 @@ properties: - description: Sleep clock source power-domains: - maxItems: 1 description: - A phandle and PM domain specifier for the MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + Phandles to OPP nodes that describe required performance point on power domains + items: + - description: MMCX performance point + - description: MXC performance point reg: maxItems: 1 @@ -80,8 +84,10 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;