| Message ID | 20250401143619.2053739-1-loic.poulain@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] arm64: dts: qcom: qcm2290: Add CCI node | expand |
On 4/1/25 4:36 PM, Loic Poulain wrote: > Add Camera Control Interface (CCI), supporting two I2C masters. > > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 44 +++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > index 7fb5de92bc4c..927dbfe61e4a 100644 > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > @@ -646,6 +646,20 @@ data-pins { > bias-pull-up; > }; > }; > + > + cci0_default: cci0-default-state { > + pins = "gpio22", "gpio23"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cci1_default: cci1-default-state { > + pins = "gpio29", "gpio30"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-disable; > + }; Please put these above the sdc pins, so that we get a by-pin-index sorting > }; > > gcc: clock-controller@1400000 { > @@ -1603,6 +1617,36 @@ adreno_smmu: iommu@59a0000 { > #iommu-cells = <2>; > }; > > + cci: cci@5c1b000 { > + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x5c1b000 0x0 0x1000>; > + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; > + clock-names = "camss_top_ahb", "cci"; > + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; > + assigned-clock-rates = <37500000>; > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; The change looks good, please update the property order / styling with this submission for x1e: https://lore.kernel.org/linux-arm-msm/20250314-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v6-4-edcb2cfc3122@linaro.org/ Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 7fb5de92bc4c..927dbfe61e4a 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -646,6 +646,20 @@ data-pins { bias-pull-up; }; }; + + cci0_default: cci0-default-state { + pins = "gpio22", "gpio23"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; }; gcc: clock-controller@1400000 { @@ -1603,6 +1617,36 @@ adreno_smmu: iommu@59a0000 { #iommu-cells = <2>; }; + cci: cci@5c1b000 { + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; + reg = <0x0 0x5c1b000 0x0 0x1000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; + clock-names = "camss_top_ahb", "cci"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; + assigned-clock-rates = <37500000>; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,qcm2290-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>;
Add Camera Control Interface (CCI), supporting two I2C masters. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)