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Wed, 2 Apr 2025 10:27:46 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 2 Apr 2025 03:27:43 -0700 From: Manikanta Mylavarapu To: , , , , , , , CC: , Subject: [PATCH v6 2/2] arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers Date: Wed, 2 Apr 2025 15:57:23 +0530 Message-ID: <20250402102723.219960-3-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402102723.219960-1-quic_mmanikan@quicinc.com> References: <20250402102723.219960-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=W6M4VQWk c=1 sm=1 tr=0 ts=67ed1123 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=vdRwA7TqO3sj12wk4UIA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: VaHASntIp8u2Umf6E1_nRB4BPPp1tfJt X-Proofpoint-GUID: VaHASntIp8u2Umf6E1_nRB4BPPp1tfJt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-02_04,2025-04-01_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 adultscore=0 mlxlogscore=809 mlxscore=0 bulkscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504020066 Enable the PCIe controller and PHY nodes corresponding to RDP466. Signed-off-by: Manikanta Mylavarapu --- Changes in V6: - No change. arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 41 ++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 0fd0ebe0251d..1f89530cb035 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -82,6 +82,32 @@ &dwc_1 { dr_mode = "host"; }; +&pcie2 { + pinctrl-0 = <&pcie2_default_state>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default_state>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie3_phy { + status = "okay"; +}; + &qusb_phy_0 { vdd-supply = <&vreg_misc_0p925>; vdda-pll-supply = <&vreg_misc_1p8>; @@ -197,6 +223,20 @@ data-pins { bias-pull-up; }; }; + + pcie2_default_state: pcie2-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + pcie3_default_state: pcie3-default-state { + pins = "gpio34"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; }; &uart1 { @@ -216,4 +256,3 @@ &usb3 { &xo_board { clock-frequency = <24000000>; }; -