@@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
bias-disable;
};
+ cci0_default: cci0-default-state {
+ pins = "gpio22", "gpio23";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
#iommu-cells = <2>;
};
+ cci: cci@5c1b000 {
+ compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x5c1b000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
+ clock-names = "camss_top_ahb", "cci";
+ assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>;
+ assigned-clock-rates = <37500000>;
+
+ power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
mdss: display-subsystem@5e00000 {
compatible = "qcom,qcm2290-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
Add Camera Control Interface (CCI), supporting two I2C masters. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> --- v2: Reorder commits; Update dts properties order and style arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)