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Thu, 17 Apr 2025 07:58:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHDWJWfJEpQ0v3xPPm3V9NntzaNWSytCeDPNAc7NMu2QmrsoAA0HpcUFuciEZHQp62F65YdHQ== X-Received: by 2002:a05:6214:410e:b0:6e8:f464:c9a0 with SMTP id 6a1803df08f44-6f2b2f3e58cmr77386816d6.13.1744901913687; Thu, 17 Apr 2025 07:58:33 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.qualcomm.com ([2a01:e0a:82c:5f0:15e4:d866:eb53:4185]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6ef48e5csm3966166b.148.2025.04.17.07.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Apr 2025 07:58:33 -0700 (PDT) From: Loic Poulain To: bryan.odonoghue@linaro.org, rfoss@kernel.org, konradybcio@kernel.org, andersson@kernel.org, krzk+dt@kernel.org, robh@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, Loic Poulain Subject: [PATCH v2 5/6] media: dt-bindings: media: camss: Add qcom,qcm2290-camss binding Date: Thu, 17 Apr 2025 16:58:18 +0200 Message-Id: <20250417145819.626733-6-loic.poulain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417145819.626733-1-loic.poulain@oss.qualcomm.com> References: <20250417145819.626733-1-loic.poulain@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=WecMa1hX c=1 sm=1 tr=0 ts=6801171b cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=XR8D0OoHHMoA:10 a=QcRrIoSkKhIA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=2DfPVCEIPBpRJJTYYFsA:9 a=1HOtulTD9v-eNWfpl4qZ:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: yJLyaYWZuAwdOI2nPzwKDYQl9KVmnXbI X-Proofpoint-ORIG-GUID: yJLyaYWZuAwdOI2nPzwKDYQl9KVmnXbI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-17_04,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504170112 Add bindings for qcom,qcm2290-camss in order to support the camera subsystem found in the Qualcomm Robotics RB1 Platform (QRB2210). Signed-off-by: Loic Poulain --- .../bindings/media/qcom,qcm2290-camss.yaml | 261 ++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml new file mode 100644 index 000000000000..1af6ed298c66 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Camera Subsystem (CAMSS) + +maintainers: + - Loic Poulain + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,qcm2290-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: vfe0 + - const: vfe1 + - const: tpg0 + - const: tpg1 + - const: top + + clocks: + maxItems: 15 + + clock-names: + items: + - const: ahb + - const: axi + - const: top_ahb + - const: csi0 + - const: csi1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy0_timer + - const: csiphy1_timer + - const: vfe0 + - const: vfe1 + - const: vfe0_cphy_rx + - const: vfe1_cphy_rx + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + + interrupts: + maxItems: 8 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: vfe0 + - const: vfe1 + - const: tpg0 + - const: tpg1 + + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + + iommus: + maxItems: 4 + + power-domains: + items: + - description: GDSC CAMSS Block, Global Distributed Switch Controller. + + vdda-phy-supply: + description: + Phandle to a 1.2V regulator supply to CSI PHYs. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to CAMSS refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@5c6e000 { + compatible = "qcom,qcm2290-camss"; + + reg = <0 0x5c6e000 0 0x1000>, + <0 0x5c75000 0 0x1000>, + <0 0x5c52000 0 0x1000>, + <0 0x5c53000 0 0x1000>, + <0 0x5c6f000 0 0x4000>, + <0 0x5c76000 0 0x4000>, + <0 0x5c66000 0 0x400>, + <0 0x5c68000 0 0x400>, + <0 0x5c11000 0 0x1000>; + reg-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "vfe0", + "vfe1", + "tpg0", + "tpg1", + "top"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + clock-names = "ahb", + "axi", + "top_ahb", + "csi0", + "csi1", + "csiphy0", + "csiphy1", + "csiphy0_timer", + "csiphy1_timer", + "vfe0", + "vfe1", + "vfe0_cphy_rx", + "vfe1_cphy_rx", + "camnoc_nrt_axi", + "camnoc_rt_axi"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "vfe0", + "vfe1", + "tpg0", + "tpg1"; + + interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc"; + + iommus = <&apps_smmu 0x400 0x0>, + <&apps_smmu 0x800 0x0>, + <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + vdda-phy-supply = <&pm4125_l5>; + vdda-pll-supply = <&pm4125_l13>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + };