From patchwork Thu May 3 11:07:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Asutosh Das (asd)" X-Patchwork-Id: 10377827 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 11831603B4 for ; Thu, 3 May 2018 11:16:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 06F3A28AFB for ; Thu, 3 May 2018 11:16:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EFCBB29080; Thu, 3 May 2018 11:16:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7AEB28AFB for ; Thu, 3 May 2018 11:16:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751913AbeECLPq (ORCPT ); Thu, 3 May 2018 07:15:46 -0400 Received: from alexa-out-tai-01.qualcomm.com ([103.229.16.226]:12748 "EHLO alexa-out-tai-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751128AbeECLOR (ORCPT ); Thu, 3 May 2018 07:14:17 -0400 X-IronPort-AV: E=Sophos;i="5.49,358,1520870400"; d="scan'208";a="443714" Received: from ironmsg02-tai.qualcomm.com ([10.249.140.7]) by alexa-out-tai-01.qualcomm.com with ESMTP; 03 May 2018 19:07:54 +0800 X-IronPort-AV: E=McAfee;i="5900,7806,8881"; a="7390445" Received: from asutoshd-linux.qualcomm.com ([10.206.24.163]) by ironmsg02-tai.qualcomm.com with ESMTP; 03 May 2018 19:07:38 +0800 Received: by asutoshd-linux.qualcomm.com (Postfix, from userid 92687) id BE6DE2E87; Thu, 3 May 2018 16:37:37 +0530 (IST) From: Asutosh Das To: subhashj@codeaurora.org, cang@codeaurora.org, vivek.gautam@codeaurora.org, rnayak@codeaurora.org, vinholikatti@gmail.com, jejb@linux.vnet.ibm.com, martin.petersen@oracle.com, asutoshd@codeaurora.org, linux-mmc@vger.kernel.org Cc: linux-scsi@vger.kernel.org, Yaniv Gardi , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 01/10] scsi: ufs: Allowing power mode change Date: Thu, 3 May 2018 16:37:13 +0530 Message-Id: <75e5ea5901004ef95b37aed719686214910f6541.1525343531.git.asutoshd@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yaniv Gardi Due to M-PHY issues, moving from HS to any other mode or gear or even Hibern8 may cause some un-predicted behavior of the device. This patch adds provides a quirk to address that. Signed-off-by: Yaniv Gardi Signed-off-by: Subhash Jadavani Signed-off-by: Can Guo Signed-off-by: Asutosh Das --- drivers/scsi/ufs/ufshcd.c | 8 +++++++- drivers/scsi/ufs/ufshcd.h | 7 +++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 5bc9dc1..f3083fe 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -4162,9 +4162,15 @@ static int ufshcd_link_startup(struct ufs_hba *hba) goto out; } while (ret && retries--); - if (ret) + if (ret) { /* failed to get the link up... retire */ goto out; + } + + if (hba->quirks & UFSHCD_QUIRK_BROKEN_PWR_MODE_CHANGE) { + ufshcd_dme_set(hba, UIC_ARG_MIB(TX_LCC_ENABLE), 0); + ufshcd_dme_set(hba, UIC_ARG_MIB(TX_LCC_ENABLE), 1); + } if (link_startup_again) { link_startup_again = false; diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index cbe46f6..bb4ecfb 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -591,6 +591,13 @@ struct ufs_hba { */ #define UFSHCD_QUIRK_PRDT_BYTE_GRAN UFS_BIT(7) + /* + * Needs to be enabled if moving from HS to any other gear/mode or even + * hibern8 causes unpredicted behavior of device. + * If this quirk is enabled, standard UFS driver will disable/enable + * TX_LCC. + */ + #define UFSHCD_QUIRK_BROKEN_PWR_MODE_CHANGE UFS_BIT(8) unsigned int quirks; /* Deviations from standard UFSHCI spec. */ /* Device deviations from standard UFS device spec. */