From patchwork Wed Dec 7 02:04:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Collins X-Patchwork-Id: 13066548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50E34C63707 for ; Wed, 7 Dec 2022 02:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229842AbiLGCFZ (ORCPT ); Tue, 6 Dec 2022 21:05:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbiLGCFY (ORCPT ); Tue, 6 Dec 2022 21:05:24 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12C7F45EF5; Tue, 6 Dec 2022 18:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1670378724; x=1701914724; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mz/oLDXD5a9DkSIPd5g99uMG+kM+zWR0kKaG8HwnncY=; b=jPIlMz1TMlVwUQidTc5lfIuparTvUQ4g+j1frgUjDH4J67uU6/YjkIyd lXEawadopWMAvZCuwzcO/DeTTv8mh1uhtaYSP4pfbXaj7fsfgMzWQPvlI 3vIhRTpEpu5Mp77blJ/cuWveHalmjkAu95U2weGCZZNMn3apqzF1mBdiv s=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 06 Dec 2022 18:05:23 -0800 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2022 18:05:23 -0800 Received: from hu-collinsd-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 6 Dec 2022 18:05:22 -0800 From: David Collins To: Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson CC: David Collins , Konrad Dybcio , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , , , Subject: [PATCH v2 1/3] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Tue, 6 Dec 2022 18:04:44 -0800 Message-ID: <96d27e38af4dd2730b3d9fec6d23d3d9a6735f57.1670375556.git.quic_collinsd@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index be785ab37e53..895a2d7bff02 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -18,6 +19,7 @@ #include "../thermal_core.h" #include "../thermal_hwmon.h" +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -73,6 +75,7 @@ struct qpnp_tm_chip { struct device *dev; struct thermal_zone_device *tz_dev; unsigned int subtype; + unsigned int dig_revision; long temp; unsigned int thresh; unsigned int stage; @@ -224,6 +227,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1]; long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown = false; + bool require_s2_shutdown = false; u8 reg; WARN_ON(!mutex_is_locked(&chip->lock)); @@ -255,9 +259,25 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n"); } + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) { + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (chip->dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + require_s2_shutdown = true; + break; + } + } + skip: reg |= chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !require_s2_shutdown) reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -372,7 +392,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; + u8 type, subtype, dig_major, dig_minor; u32 res; int ret, irq; @@ -428,6 +448,14 @@ static int qpnp_tm_probe(struct platform_device *pdev) return ret; } + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) { + dev_err(&pdev->dev, "could not read dig_minor\n"); + return ret; + } + + chip->dig_revision = (dig_major << 8) | dig_minor; + if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 && subtype != QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",