From patchwork Sat Aug 17 07:12:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Glocker X-Patchwork-Id: 13767021 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B27820E6; Sat, 17 Aug 2024 07:12:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878733; cv=none; b=oNONpA7RVanqN7TNDguMJbJ2qwcoHtgdRRrd/bFdKrSOkqkpuZnn0w4H9wbI0stKUW9+drKGRT/I98vpqgpnsMO4PSWpLz4VgSYAUASStwLfPGTB6ToLVF1nwRJoBt5o2N9KPvnShrww6cR+UfgkLFttcbS8l7LHBl57eZgv01o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878733; c=relaxed/simple; bh=RUP6Gqoj9OT0gB/mLdkcHmKdOD4LZB/wGNIcRzaeELo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hXDdqPKmEjJioFX9sZPbKOF3r++L3MJsonG6aGSWCbHSa4AEgMNzsSN45VYK2HiR3yekhFSsL1uP584AKSBoX8IoyosHhGU6YxWa0w2G6sLth15CCysy2tQZ3pWUH2+VIcCETKStqHmENj+3+JoWSJJpmzo1YkAXkR3Da2czJvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id 45b17932; Sat, 17 Aug 2024 09:12:09 +0200 (CEST) Date: Sat, 17 Aug 2024 09:12:09 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 4/6] arm64: dts: qcom: Add UFS node Message-ID: References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Add the ufs host controller node for the Qualcomm X1E80100. This was copied from arch/arm64/boot/dts/qcom/sc7180.dtsi and adapted to our needs. Signed-off-by: Marcus Glocker --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 7bca5fcd7d52..235e20e4b51f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2878,6 +2878,77 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,x1e80100-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xa0 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ice = <&ice>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,x1e80100-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + + ice: crypto@1d90000 { + compatible = "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + pcie6a: pci@1bf8000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100";