From patchwork Fri Sep 14 21:48:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5EBAE14DA for ; Sat, 15 Sep 2018 00:17:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 381E82BA4C for ; Sat, 15 Sep 2018 00:17:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BC572BA53; Sat, 15 Sep 2018 00:17:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A478F2BA4C for ; Sat, 15 Sep 2018 00:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725796AbeIOFd6 (ORCPT ); Sat, 15 Sep 2018 01:33:58 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18510 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725754AbeIOFd6 (ORCPT ); Sat, 15 Sep 2018 01:33:58 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 17:17:17 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 17:17:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 17:17:13 -0700 Received: from tbergstrom-lnx.Nvidia.com (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 15 Sep 2018 00:17:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 4851FF836CE; Sat, 15 Sep 2018 00:48:16 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 00/14] Tegra210 EMC scaling Date: Sat, 15 Sep 2018 00:48:01 +0300 Message-ID: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536970637; bh=WfO53tDAnz33DismbmIHB/V/P7rM7x2yKa7cvYkaV9A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type:X-Originating-IP: X-ClientProxiedBy; b=beJoQZIcN10iZ+4a6v5532feTnMbs0sL+hjbHNaVfwk9rLZ99AnFwTv63uJTxcVNe elqCsc8Vd+21R4rJmgnZvsoTSKdf99er5Ayfv8zXoL+zE6CJkMBOig8pcejOETBtEk X9m3W7GWluoVdEIKhWdRyBc4Kdpqf/d1H/Dsm2ntmcrs7PRAEEH8Fd6KV9WT1yjKp6 4z8BwcrR0jvFxIpcJ/NzcdCGU7kGkRN012/GVVIjgA3tegXTHFteHG6IQr723z90GP QiGlQ06V6Lq6HB3iAzk/ghRW8nqYfeMvKWbDR+aHqN8L8C8jPgguudL7P63UHauFkn T8y+boUg3mdww== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This series introduces EMC scaling for Tegra210. It's a preliminary version which hasn't been extensively tested so it may crash your system. The reason I'm posting it anyway to start discussing the DT binding document. The problem here is that this binding is also used by firmware which is already in the field. The firmware needs the data in the DT to perform the initial training and it also writes the results of this training in the DT which are then used by this driver. Without this training higher OPPs cannot be used. Peter De Schrijver (14): memory: tegra: mc: Add Tegra210 MC emem registers clk: tegra: rename emc timing functions clk: tegra: emc: simplify parent matching clk: tegra: emc: prepare for Tegra210 parent table memory: tegra: mc: Introduce helpers memory: tegra: mc: Add support for scaled LA memory: tegra: scaled LA register for Tegra210 clk: tegra: clock changes for emc scaling memory: tegra: Add definitions shared by Tegra210 EMC scaling code memory: tegra: Add Tegra210 EMC scaling sequence memory: tegra: parse DT and costruct timing tables memory: tegra: Tegra210 EMC memory driver memory: tegra: enable Tegra210 EMC scaling driver dt-bindings: tegra: Add Tegra210 EMC binding .../memory-controllers/nvidia,tegra210-emc.txt | 448 ++++ drivers/clk/tegra/clk-emc.c | 88 +- drivers/clk/tegra/clk-tegra210.c | 53 +- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 84 +- drivers/memory/tegra/tegra124-emc.c | 8 +- drivers/memory/tegra/tegra210-dt-parse.c | 363 ++++ drivers/memory/tegra/tegra210-emc-cc-r21021.c | 1864 ++++++++++++++++ drivers/memory/tegra/tegra210-emc-reg.h | 1879 ++++++++++++++++ drivers/memory/tegra/tegra210-emc.c | 2268 ++++++++++++++++++++ drivers/memory/tegra/tegra210.c | 99 + include/dt-bindings/clock/tegra210-car.h | 2 + include/soc/tegra/emc.h | 8 +- include/soc/tegra/mc.h | 6 + 15 files changed, 7119 insertions(+), 62 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt create mode 100644 drivers/memory/tegra/tegra210-dt-parse.c create mode 100644 drivers/memory/tegra/tegra210-emc-cc-r21021.c create mode 100644 drivers/memory/tegra/tegra210-emc-reg.h create mode 100644 drivers/memory/tegra/tegra210-emc.c