From patchwork Mon Jul 23 21:54:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 10541185 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C63F6112E for ; Mon, 23 Jul 2018 21:54:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B62BB28538 for ; Mon, 23 Jul 2018 21:54:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9C682856A; Mon, 23 Jul 2018 21:54:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 50A2A28538 for ; Mon, 23 Jul 2018 21:54:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388104AbeGWW5p (ORCPT ); Mon, 23 Jul 2018 18:57:45 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:44340 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388077AbeGWW5o (ORCPT ); Mon, 23 Jul 2018 18:57:44 -0400 Received: by mail-pl0-f65.google.com with SMTP id m16-v6so777321pls.11 for ; Mon, 23 Jul 2018 14:54:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=AiMcsDISjo+rzdirtL4WDbw9pifJkrp+ppqWPXfySSE=; b=EDZMIFhoJana0AYDWztdQGzZqE4qvRoUal/3fv0aT1r5u5yranHNP40n75/62LEDmD CMmtgAkKrL6w2+f0PvrTLcf5pwHPj25rtSVliIodsEdPwoWLIS8/vXD9I1PzBUNNSIRg xSrcDRkYpT7lGIGrrVZ/G1BVePhldd3dLkZUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=AiMcsDISjo+rzdirtL4WDbw9pifJkrp+ppqWPXfySSE=; b=aOD9m3N/N3PmVDo6rEoYytzfIQ6E7dFNoy49/CBtNfo/H6vfuNSfaYBS7Ko00FNUfK pJVOEwq1JOxec0fYbc2hsLq0NEQsEZPyBFl165eq9K1FFoU3Vpi8wbHRfL/4rP/ZKHkd V20UH1oXwGmhmqZM4SKAboQpfUEIoXBql+39lbQ29yLNzchMnMDQnQ1egE6OyAdHWyh7 wFYuDZCQl/Zw4FH6hssvCnNyeZW9dowWqpvoHGSOaDXUKV7LQ53FvUylZLi3bd84DbW7 qJz/6yTponQEuEP0QQiz7f8WPbl67FCGbLJc64XteCPC0O97xMN5p1NR/osHAyDrjnax D5oA== X-Gm-Message-State: AOUpUlFXMLM8jazdYZZ5OELnTGtWxLcT4JwJ+5f78yR4akkfWoeBkcjI c0CRci7K1I9ZJ4ouEr4NoxaQhg== X-Google-Smtp-Source: AAOMgpdFMsN8idRc4ZUSflNDqDYkMszi4DH0Gkg6YunIVxXi+YEsq8BC/+QECR3K5YUnUbjGNni4dg== X-Received: by 2002:a17:902:8697:: with SMTP id g23-v6mr14384628plo.292.1532382871603; Mon, 23 Jul 2018 14:54:31 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:0:1000:1501:38e4:86fe:ec0c:4007]) by smtp.gmail.com with ESMTPSA id n26-v6sm5927629pgv.78.2018.07.23.14.54.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jul 2018 14:54:30 -0700 (PDT) From: Douglas Anderson To: sboyd@kernel.org, andy.gross@linaro.org Cc: tdas@codeaurora.org, grahamr@codeaurora.org, girishm@codeaurora.org, anischal@codeaurora.org, bjorn.andersson@linaro.org, Douglas Anderson , devicetree@vger.kernel.org, Michael Turquette , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, David Brown , Rob Herring , Mark Rutland , linux-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 0/2] clk: qcom: Quad SPI (qspi) clock support for sdm845 Date: Mon, 23 Jul 2018 14:54:02 -0700 Message-Id: <20180723215404.74296-1-dianders@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This two-series patch adds the needed clock bits to use the Quad SPI (qspi) part on sdm845. It's expected that the bindings part of this patch could land in the clock tree with an immutable git hash and then be pulled into the Qualcomm tree so it could be used by dts files. From the reply to my v1, the clock plan for this clock is: - MinSVS@19.2 - LowSVS@75 - SVS@150 - Nominal@300 ...and intermediate frequencies can be used at frequences less than 300. I didn't see a need for 75 MHz and it was unclear from previous replies if this should come from MAIN or EVEN so I left it out. I have added 100 MHz here since it is useful (/ 4 = 25 MHz is a useful clock for SPI flash) OTHER NOTES: - From probing lines, it appears that the Quad SPI block has a divide by 4 somewhere inside it (probably so it can oversample the lines, or possibly so it can generate phase-offset clocks). Thus we need the core to go 4 times faster than we'd expect to run the SPI bus. - SPI devices usually specify the MAX frequency they should be clocked at, so it's important that we use the clk_rcg2_floor_ops here rather than the clk_rcg2_ops Changes in v2: - Only 19.2, 100, 150, and 300 MHz now. - All clocks come from MAIN rather than EVEN. - Use parent map 0 instead of new parent map 9. Douglas Anderson (2): clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header clk: qcom: Add qspi (Quad SPI) clocks for sdm845 drivers/clk/qcom/gcc-sdm845.c | 63 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 3 + 2 files changed, 66 insertions(+)