| Message ID | 20200310152003.2945170-1-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add EMC scaling support for Tegra210 | expand |
10.03.2020 18:20, Thierry Reding пишет: > From: Joseph Lo <josephl@nvidia.com> > > This is the initial patch for Tegra210 EMC frequency scaling. It has the > code to program various aspects of the EMC that are standardized, but it > does not yet include the specific programming sequence needed for clock > scaling. > > The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 > need to perform training of the RAM before it can be used. Firmware will > perform this training during early boot and pass a table of supported > frequencies to the kernel via device tree. > > For the frequencies above 800 MHz, periodic retraining is needed to > compensate for changes in timing. This periodic training will have to be > performed until the frequency drops back to or below 800 MHz. > > This driver provides helpers used during this runtime retraining that > will be used by the sequence specific code in a follow-up patch. > > Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v5: > - major rework and cleanup > > drivers/memory/tegra/tegra210-emc.c | 1952 +++++++++++++++++++++------ > drivers/memory/tegra/tegra210-emc.h | 893 +++++++++++- > 2 files changed, 2390 insertions(+), 455 deletions(-) > > diff --git a/drivers/memory/tegra/tegra210-emc.c b/drivers/memory/tegra/tegra210-emc.c > index 80ea14d1e6ce..4ea8fb70a4fd 100644 > --- a/drivers/memory/tegra/tegra210-emc.c > +++ b/drivers/memory/tegra/tegra210-emc.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. > + * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. > */ Would be nice to avoid all the unnecessary changes, like the one above and then all the code's removals/reshuffling. Such that a new patch was a clean addition to a previous patch, instead of a re-write.
On Tue, Mar 10, 2020 at 07:43:12PM +0300, Dmitry Osipenko wrote: > 10.03.2020 18:20, Thierry Reding пишет: > > From: Joseph Lo <josephl@nvidia.com> > > > > This is the initial patch for Tegra210 EMC frequency scaling. It has the > > code to program various aspects of the EMC that are standardized, but it > > does not yet include the specific programming sequence needed for clock > > scaling. > > > > The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 > > need to perform training of the RAM before it can be used. Firmware will > > perform this training during early boot and pass a table of supported > > frequencies to the kernel via device tree. > > > > For the frequencies above 800 MHz, periodic retraining is needed to > > compensate for changes in timing. This periodic training will have to be > > performed until the frequency drops back to or below 800 MHz. > > > > This driver provides helpers used during this runtime retraining that > > will be used by the sequence specific code in a follow-up patch. > > > > Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. > > > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > Changes in v5: > > - major rework and cleanup > > > > drivers/memory/tegra/tegra210-emc.c | 1952 +++++++++++++++++++++------ > > drivers/memory/tegra/tegra210-emc.h | 893 +++++++++++- > > 2 files changed, 2390 insertions(+), 455 deletions(-) > > > > diff --git a/drivers/memory/tegra/tegra210-emc.c b/drivers/memory/tegra/tegra210-emc.c > > index 80ea14d1e6ce..4ea8fb70a4fd 100644 > > --- a/drivers/memory/tegra/tegra210-emc.c > > +++ b/drivers/memory/tegra/tegra210-emc.c > > @@ -1,6 +1,6 @@ > > // SPDX-License-Identifier: GPL-2.0 > > /* > > - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. > > + * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. > > */ > > Would be nice to avoid all the unnecessary changes, like the one above > and then all the code's removals/reshuffling. > > Such that a new patch was a clean addition to a previous patch, instead > of a re-write. I think this is the result of me messing up a rebase. The EMC driver changes added in the clock driver patch should've been in this patch, which would've made this a clean addition. I'll reshuffle the code for the next revision. Thanks for pointing that out. Thierry
10.03.2020 18:20, Thierry Reding пишет: > From: Joseph Lo <josephl@nvidia.com> > > This is the initial patch for Tegra210 EMC frequency scaling. It has the > code to program various aspects of the EMC that are standardized, but it > does not yet include the specific programming sequence needed for clock > scaling. > > The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 > need to perform training of the RAM before it can be used. Firmware will > perform this training during early boot and pass a table of supported > frequencies to the kernel via device tree. > > For the frequencies above 800 MHz, periodic retraining is needed to > compensate for changes in timing. This periodic training will have to be > performed until the frequency drops back to or below 800 MHz. > > This driver provides helpers used during this runtime retraining that > will be used by the sequence specific code in a follow-up patch. > > Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v5: > - major rework and cleanup > ... > #include "mc.h" > > +#define DVFS_FGCG_HIGH_SPEED_THRESHOLD 1000 > +#define IOBRICK_DCC_THRESHOLD 2400 > +#define DVFS_FGCG_MID_SPEED_THRESHOLD 600 > + > +#define EMC_STATUS_UPDATE_TIMEOUT 1000 > + > +#define MC_EMEM_ADR_CFG 0x54 > +#define MC_EMEM_ARB_CFG 0x90 > +#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 > +#define MC_EMEM_ARB_TIMING_RCD 0x98 > +#define MC_EMEM_ARB_TIMING_RP 0x9c > +#define MC_EMEM_ARB_TIMING_RC 0xa0 > +#define MC_EMEM_ARB_TIMING_RAS 0xa4 > +#define MC_EMEM_ARB_TIMING_FAW 0xa8 > +#define MC_EMEM_ARB_TIMING_RRD 0xac > +#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 > +#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 > +#define MC_EMEM_ARB_TIMING_R2R 0xb8 > +#define MC_EMEM_ARB_TIMING_W2W 0xbc > +#define MC_EMEM_ARB_TIMING_R2W 0xc0 > +#define MC_EMEM_ARB_TIMING_W2R 0xc4 > +#define MC_EMEM_ARB_MISC2 0xc8 > +#define MC_EMEM_ARB_DA_TURNS 0xd0 > +#define MC_EMEM_ARB_DA_COVERS 0xd4 > +#define MC_EMEM_ARB_MISC0 0xd8 > +#define MC_EMEM_ARB_MISC1 0xdc > +#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 All these registers are already defined in mc.h, please don't re-define them. > +#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 > +#define MC_LATENCY_ALLOWANCE_HC_0 0x310 > +#define MC_LATENCY_ALLOWANCE_HC_1 0x314 > +#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 > +#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 > +#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 > +#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 > +#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 > +#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 > +#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c > +#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 > +#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 > +#define MC_LATENCY_ALLOWANCE_VIC_0 0x394 > +#define MC_LATENCY_ALLOWANCE_VI2_0 0x398 > +#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac > +#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 > +#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc > +#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 > +#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 > +#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8 > +#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 > +#define MC_MLL_MPCORER_PTSA_RATE 0x44c > +#define MC_FTOP_PTSA_RATE 0x50c > +#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 > +#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 > +#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 > +#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 > +#define MC_PTSA_GRANT_DECREMENT 0x960 > +#define MC_EMEM_ARB_DHYST_CTRL 0xbcc > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 > +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec... Secondly, looks like it all is unused, hence just remove it.
From: Thierry Reding <treding@nvidia.com> This series introduces the EMC clock scaling support for Tegra210. The EMC table of supported frequencies is passed to the kernel via a device tree reserved memory region. Joseph posted the v4 of this series[0] about a year ago. I've dusted it off a bit and tried to address all of the comments that Dmitry had made in response to v4. Changes in v4: - major rework to split this into a clk driver and an EMC driver - refactored some code to remove duplication and improve readability - removed some unused code and variables Thierry [0]: https://lore.kernel.org/linux-arm-kernel/20190529082139.5581-1-josephl@nvidia.com/ Joseph Lo (8): clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Export functions for EMC clock scaling clk: tegra: Implement Tegra210 EMC clock dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 memory: tegra: Add EMC scaling support code for Tegra210 memory: tegra: Add EMC scaling sequence code for Tegra210 arm64: tegra: Add external memory controller node for Tegra210 clk: tegra: Remove the old emc_mux clock for Tegra210 .../nvidia,tegra210-emc.yaml | 83 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 + drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra210-emc.c | 352 ++++ drivers/clk/tegra/clk-tegra210.c | 83 +- drivers/clk/tegra/clk.h | 3 + drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra210-emc-cc-r21021.c | 1782 ++++++++++++++++ drivers/memory/tegra/tegra210-emc.c | 1800 +++++++++++++++++ drivers/memory/tegra/tegra210-emc.h | 1065 ++++++++++ include/dt-bindings/clock/tegra210-car.h | 4 +- include/linux/clk/tegra.h | 26 + 13 files changed, 5202 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml create mode 100644 drivers/clk/tegra/clk-tegra210-emc.c create mode 100644 drivers/memory/tegra/tegra210-emc-cc-r21021.c create mode 100644 drivers/memory/tegra/tegra210-emc.c create mode 100644 drivers/memory/tegra/tegra210-emc.h