From patchwork Wed Dec 9 19:53:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 11962413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B4A8C433FE for ; Wed, 9 Dec 2020 19:54:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2090023A7C for ; Wed, 9 Dec 2020 19:54:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729922AbgLITyy (ORCPT ); Wed, 9 Dec 2020 14:54:54 -0500 Received: from bin-mail-out-06.binero.net ([195.74.38.229]:41385 "EHLO bin-mail-out-06.binero.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727750AbgLITyy (ORCPT ); Wed, 9 Dec 2020 14:54:54 -0500 X-Halon-ID: 49d4e69e-3a58-11eb-a542-005056917a89 Authorized-sender: niklas.soderlund@fsdn.se Received: from bismarck.berto.se (p4fca2458.dip0.t-ipconnect.de [79.202.36.88]) by bin-vsp-out-01.atm.binero.net (Halon) with ESMTPA id 49d4e69e-3a58-11eb-a542-005056917a89; Wed, 09 Dec 2020 20:54:12 +0100 (CET) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Geert Uytterhoeven , linux-clk@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 0/5] clk: renesas: Add TMU clocks Date: Wed, 9 Dec 2020 20:53:38 +0100 Message-Id: <20201209195343.803120-1-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi, This series adds the missing TMU clocks for most Renesas R-Car Gen3 SoCs. I have tested this series on all boards but D3 and E3 as I do not have access to those. But I see no reason they should not not work equally well as they the boards I can test on. Niklas Söderlund (5): clk: renesas: r8a7795: Add TMU clocks clk: renesas: r8a7796: Add TMU clocks clk: renesas: r8a77965: Add TMU clocks clk: renesas: r8a77990: Add TMU clocks clk: renesas: r8a77995: Add TMU clocks drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 +++++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++++ drivers/clk/renesas/r8a77965-cpg-mssr.c | 5 +++++ drivers/clk/renesas/r8a77990-cpg-mssr.c | 5 +++++ drivers/clk/renesas/r8a77995-cpg-mssr.c | 5 +++++ 5 files changed, 25 insertions(+)