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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id h7sm3144847edt.37.2021.10.21.10.42.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 10:42:31 -0700 (PDT) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , linux-kernel@vger.kernel.org Subject: [PATCH v2 00/16] Basic StarFive JH7100 RISC-V SoC support Date: Thu, 21 Oct 2021 19:42:07 +0200 Message-Id: <20211021174223.43310-1-kernel@esmil.dk> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This series adds support for the StarFive JH7100 RISC-V SoC. The SoC has many devices that need non-coherent dma operations to work which isn't upstream yet[1], so this just adds basic support to boot up, get a serial console, blink an LED and reboot itself. Unlike the Allwinner D1 this chip doesn't use any extra pagetable bits, but instead the DDR RAM appears twice in the memory map, with and without the cache. The JH7100 is a test chip for the upcoming JH7110 and about 300 BeagleV Starlight Beta boards were sent out with them as part of a now cancelled BeagleBoard.org project. However StarFive has produced more of the JH7100s and more boards will be available[2] to buy. Hopefully before the end of the year. This series is also available at https://github.com/esmil/linux/commits/starlight-minimal ..but a more complete kernel including drivers for non-coherent peripherals based on this series can be found at https://github.com/starfive-tech/linux/tree/starlight [1]: https://lore.kernel.org/linux-riscv/20210723214031.3251801-2-atish.patra@wdc.com/ [2]: https://www.linkedin.com/pulse/starfive-release-open-source-single-board-platform-q3-2021-starfive/ /Emil Changes since v1: - Let SOC_STARFIVE select RESET_CONTROLLER but drop SERIAL_8250_DW - Add missing Signed-of-by to clock dt-binding header - Use builtin_platform_driver macro for the clock driver, add explicit comment to the determine_rate callback and other small nits from Andy - Use reset-controller for node names in documentation and device tree - Use readl_poll_timeout in reset driver to avoid hanging forever if a driver leaves the associated clock gated and sort Kconfig and Makefile entries properly. - In the pinctrl driver align register names with documentation, remove invalid __init tag from probe function, use of_property_* functions to parse device tree, hoist pinmux unpacking into helper function to better document what's going on, bail on invalid signal group in device tree and fix many other nits from Andy. - Refactor and rebase 8250_dw quirk on tty-next Emil Renner Berthing (12): RISC-V: Add StarFive SoC Kconfig option dt-bindings: timer: Add StarFive JH7100 clint dt-bindings: interrupt-controller: Add StarFive JH7100 plic dt-bindings: reset: Add Starfive JH7100 reset bindings reset: starfive-jh7100: Add StarFive JH7100 reset driver dt-bindings: pinctrl: Add StarFive pinctrl definitions dt-bindings: pinctrl: Add StarFive JH7100 bindings pinctrl: starfive: Add pinctrl driver for StarFive SoCs dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts serial: 8250_dw: Add skip_clk_set_rate quirk RISC-V: Add initial StarFive JH7100 device tree RISC-V: Add BeagleV Starlight Beta device tree Geert Uytterhoeven (4): dt-bindings: clock: starfive: Add JH7100 clock definitions dt-bindings: clock: starfive: Add JH7100 bindings clk: starfive: Add JH7100 clock generator driver dt-bindings: reset: Add StarFive JH7100 reset definitions .../clock/starfive,jh7100-clkgen.yaml | 56 + .../sifive,plic-1.0.0.yaml | 1 + .../pinctrl/starfive,jh7100-pinctrl.yaml | 274 ++++ .../bindings/reset/starfive,jh7100-reset.yaml | 38 + .../bindings/serial/snps-dw-apb-uart.yaml | 5 + .../bindings/timer/sifive,clint.yaml | 1 + MAINTAINERS | 22 + arch/riscv/Kconfig.socs | 8 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/starfive/Makefile | 2 + .../dts/starfive/jh7100-beaglev-starlight.dts | 162 ++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 228 +++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 9 + drivers/clk/starfive/Makefile | 3 + drivers/clk/starfive/clk-starfive-jh7100.c | 776 +++++++++ drivers/pinctrl/Kconfig | 16 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-starfive.c | 1387 +++++++++++++++++ drivers/reset/Kconfig | 8 + drivers/reset/Makefile | 1 + drivers/reset/reset-starfive-jh7100.c | 165 ++ drivers/tty/serial/8250/8250_dw.c | 19 +- include/dt-bindings/clock/starfive-jh7100.h | 202 +++ .../dt-bindings/pinctrl/pinctrl-starfive.h | 274 ++++ include/dt-bindings/reset/starfive-jh7100.h | 126 ++ 27 files changed, 3784 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml create mode 100644 arch/riscv/boot/dts/starfive/Makefile create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.c create mode 100644 drivers/pinctrl/pinctrl-starfive.c create mode 100644 drivers/reset/reset-starfive-jh7100.c create mode 100644 include/dt-bindings/clock/starfive-jh7100.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive.h create mode 100644 include/dt-bindings/reset/starfive-jh7100.h