From patchwork Sun May 1 08:34:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12833554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E456C433EF for ; Sun, 1 May 2022 08:34:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240571AbiEAIiV (ORCPT ); Sun, 1 May 2022 04:38:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238320AbiEAIiV (ORCPT ); Sun, 1 May 2022 04:38:21 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 279DF1AF1C; Sun, 1 May 2022 01:34:56 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,189,1647270000"; d="scan'208";a="118507028" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 01 May 2022 17:34:55 +0900 Received: from localhost.localdomain (unknown [10.226.92.14]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B083A4006CD0; Sun, 1 May 2022 17:34:52 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 0/4] Add RZ/G2UL CLK and Reset entries for RSPI,TSU,ADC and SPI Multi IO Bus Controller Date: Sun, 1 May 2022 09:34:46 +0100 Message-Id: <20220501083450.26541-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch series aims to add CLK and Reset entries for SPI Multi I/O Bus Controller,RSPI,TSU and ADC found on RZ/G2UL SoC to RZ/G2L CPG driver. Biju Das (4): clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller clk: renesas: r9a07g043: Add RSPI clock and reset entries clk: renesas: r9a07g043: Add TSU clock and reset entry clk: renesas: r9a07g043: Add clock and reset entries for ADC drivers/clk/renesas/r9a07g043-cpg.c | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)