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Sat, 30 Mar 2024 18:28:53 GMT Received: from hu-ajipan-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sat, 30 Mar 2024 11:28:48 -0700 From: Ajit Pandey To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy CC: , , , Taniya Das , "Jagadeesh Kona" , Imran Shaik , "Satya Priya Kakitapalli" , Ajit Pandey Subject: [PATCH 0/7] clk: qcom: Add support for DISPCC, CAMCC and GPUCC on SM4450 Date: Sat, 30 Mar 2024 23:58:10 +0530 Message-ID: <20240330182817.3272224-1-quic_ajipan@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sRYa_RqwOHLtIE8ntR76mUi-gpP2u1pv X-Proofpoint-ORIG-GUID: sRYa_RqwOHLtIE8ntR76mUi-gpP2u1pv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-30_13,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1011 adultscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 mlxlogscore=945 impostorscore=0 spamscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403300151 This patch series add dt-bindings and driver support for DISPCC, CAMCC and GPUCC on QCOM SM4450 platform and also includes a fix related to LUCID EVO PLL config issue in clk-alpha-pll driver. Ajit Pandey (7): clk: qcom: clk-alpha-pll: Fix CAL_L_VAL override for LUCID EVO PLL dt-bindings: clock: qcom: Add DISPCC clocks for SM4450 clk: qcom: Add DISPCC driver support for SM4450 dt-bindings: clock: qcom: Add CAMCC clocks for SM4450 clk: qcom: Add CAMCC driver support for SM4450 dt-bindings: clock: qcom: Add GPUCC clocks for SM4450 clk: qcom: Add GPUCC driver support for SM4450 .../bindings/clock/qcom,sm4450-camcc.yaml | 63 + .../bindings/clock/qcom,sm4450-dispcc.yaml | 71 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + drivers/clk/qcom/Kconfig | 27 + drivers/clk/qcom/Makefile | 3 + drivers/clk/qcom/camcc-sm4450.c | 1688 +++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 2 +- drivers/clk/qcom/dispcc-sm4450.c | 781 ++++++++ drivers/clk/qcom/gpucc-sm4450.c | 806 ++++++++ include/dt-bindings/clock/qcom,sm4450-camcc.h | 106 ++ .../dt-bindings/clock/qcom,sm4450-dispcc.h | 51 + include/dt-bindings/clock/qcom,sm4450-gpucc.h | 62 + 12 files changed, 3661 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml create mode 100644 drivers/clk/qcom/camcc-sm4450.c create mode 100644 drivers/clk/qcom/dispcc-sm4450.c create mode 100644 drivers/clk/qcom/gpucc-sm4450.c create mode 100644 include/dt-bindings/clock/qcom,sm4450-camcc.h create mode 100644 include/dt-bindings/clock/qcom,sm4450-dispcc.h create mode 100644 include/dt-bindings/clock/qcom,sm4450-gpucc.h