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AJvYcCV/9Gw1br/cUD8YTSSnkc75ftnkqkzU+dOuEMNPN889w6/bBZuZdqmtFEBoWXIMPPlSYnXKTuHKk7A=@vger.kernel.org, AJvYcCV9FcC9awL0GJ7C+o1IWfv7+ZYoH1vubdNToU4LMXixVVAJfnBTYeF4rx8e+OFhKLGe057ZSudpZH/TX/Fh@vger.kernel.org X-Gm-Message-State: AOJu0YxDe94sqoiJUOdJ65nAQojjIKhbOwMYRo+F+KjPG948R1QAKSLB ZiPh4FBh73Wzwx0UW3T/TEMCsjV3Oh4RZc4rQUss35qTTbT7ZlmC X-Google-Smtp-Source: AGHT+IEpsZdR/mnaGMNQLn/MYL46svVGXIjUPQt4XnItVARSLKGHdQuYG4gZj4WquWP6KXgaYlq0+w== X-Received: by 2002:a17:907:f15e:b0:a86:b923:4a04 with SMTP id a640c23a62f3a-a870aafff64mr107463066b.50.1724837908939; Wed, 28 Aug 2024 02:38:28 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:5ac5:89a0:20cd:42bc]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a86e548967fsm222634366b.19.2024.08.28.02.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 02:38:28 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 0/2] clk: renesas: rzv2h-cpg: Add divider clock support Date: Wed, 28 Aug 2024 10:38:20 +0100 Message-Id: <20240828093822.162855-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Hi All, This patch series aims to add divider clock support and add clock and reset entries for below IP blocks for RZ/V2H(P) SoC, - GTM - WDT - RIIC - SDHI v2->v3 - Updated DDIV_DIVCTL_WEN() macro - Introduced struct ddiv to pass divider config - Updated DDIV_PACK() macro v1->v2 - Updated DDIV_PACK macro to accommodate width and dropped DDIV_DIVCTL_WIDTH - Updated DDIV_GET_* macros - Now doing rmw as some of the DIVCTLx require it Cheers, Prabhakar Lad Prabhakar (2): clk: renesas: rzv2h-cpg: Add support for dynamic switching divider clocks clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT drivers/clk/renesas/r9a09g057-cpg.c | 84 ++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 165 +++++++++++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 43 +++++++- 3 files changed, 289 insertions(+), 3 deletions(-)