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Date: Fri, 25 Oct 2024 14:22:52 +0530 Message-ID: <20241025-sa8775p-mm-v4-resend-patches-v6-0-329a2cac09ae@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAGRcG2cC/32OsQ7CIBRFf8W82WeAQqlO/ofpQODVMpRWqETT9 N/FGuPmeO5wzl0gUfSU4LRbIFL2yY+hQL3fge1NuBJ6VxgEE5IzzjCZRms14TBglhgpUXA4mdn 2lFAKXSlHnRKGQVFMkTr/2PSX9sORbvdSmX9j79M8xud2Iav3+q3x/7WskKE0x45rZ+umMueit j7Ygx0HaNd1fQFs3q/z3wAAAA== X-Change-ID: 20241010-sa8775p-mm-v4-resend-patches-42735def52a0 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , Bartosz Golaszewski CC: , , , , Ajit Pandey , Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: I6QJeOy8ZQU_Yg5KF14Ng8oAUm70xYBw X-Proofpoint-ORIG-GUID: I6QJeOy8ZQU_Yg5KF14Ng8oAUm70xYBw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250068 [v6] Update commit subject and commit message for both the DT patches [Bjorn] Subset of the patch series applied: (Removed from this series) Link to v5: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com [v5] Rebased the device tree patch to add clock controller nodes. [v4] Changes in [v4] compared to [v3] Videocc: Update the mvs0/mvs1 gdsc to use HW_CTRL_TRIGGER [Konrad and Qualcomm internal discussions] Camcc: Add new clock to the clock tree. Change the patch order for 'Update sleep_clk frequency to 32000 on SA8775P' [Krzysztof] Changes in [v3] compared to [v2]: Update the qcom_cc_really_probe() to use &pdev->dev, for the CAMCC, DISPCC & VIDEOCC drivers. [v2] https://lore.kernel.org/all/20240612-sa8775p-mm-clock-controllers-v1-0-db295a846ee7@quicinc.com/ Changes in [v2] compared to [v1]: [PATCH 1/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 3/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 5/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 7/8]: Split updating sleep_clk frequency to separate patch [PATCH 8/8]: Newly added to update sleep_clk frequency to 32000 These multimedia clock controller and device tree patches are split from the below [v1] series. [v1] https://lore.kernel.org/all/20240531090249.10293-1-quic_tdas@quicinc.com/ Signed-off-by: Taniya Das --- Taniya Das (2): arm64: dts: qcom: sa8775p: Update sleep_clk frequency arm64: dts: qcom: sa8775p: Add support for clock controllers arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 57 ++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 1 deletion(-) --- base-commit: 0cca97bf23640ff68a6e8a74e9b6659fdc27f48c change-id: 20241010-sa8775p-mm-v4-resend-patches-42735def52a0 Best regards,