From patchwork Fri Nov 8 04:09:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13867506 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B7063BBEA; Fri, 8 Nov 2024 04:10:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731039024; cv=none; b=uQHQcuoENLDc+PLua3d3vzfdkO85cK8U1EwRO4lfvmp3uZ85wA9Bm7r5xS+Df8BD2sDng7eOqpAWCyauU80aktFTYbatSuDcMn3H+lv3lS156RZqhInobBXp/DZ4WmqcQkKbA+j74OmbTdbVsxfpDndo5qMkpW6zHa5iywq9Hvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731039024; c=relaxed/simple; bh=l65LaPZ9RxTtpSm1nyOzcq0VVZW2s+9T2l7JFa1JPUI=; h=From:Subject:Date:Message-ID:MIME-Version:Content-Type:To:CC; b=kUM9TupUi8bK5hccgBClEk5NvAGDvOf1K4Pv1gs0mTLor7sjI3NOxHR1N2aIpnWyupjzQags7y5xwhwzGL7BA525VYYZbFZxXmB0oLM3tWTynCp3m57FtcFHEXVCrpC5HiO0qjT3WJLLoadihNk7ZEIR5iaL9acH2BTSflydlO8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=KP3+hZSE; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KP3+hZSE" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MamnM030533; Fri, 8 Nov 2024 04:09:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=KCqA6joE3Mjqka2gpR/xTV o2oiBQLH3TN70A1xAD6rc=; b=KP3+hZSEfbwdKwzegW6ac3Dd6+YA/tQGAUcxjy CRvM9fVlU/dkANCrZXSC2TmPVwfPd4YIKtd5ksPXl6F6ZymU84nwqwND6xj+CVb6 OzC2B9ezp/uU8bRW8mI9zX9NlscAa+h5nE/srvbnZzbHIX8Px3OF+4bsZLXPlqJd Z9LgXxwib+ayj2anqixyfHe60Me7C2eek2JE9aJvAPbvTBM7uElfR0drwphOp6q1 vrAD9A/mcDgSjUzWmDLtBBRt62KS6Iri9CzxDHbc9Jd4hkKVk3zW238Ve8XTJ1dq U9AyltIlHH/bd4HAejWfSuQew8kueG02gN4u5eXV5YwC26+g== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gdrkmg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Nov 2024 04:09:42 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A849fm1016723 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 8 Nov 2024 04:09:41 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 20:09:35 -0800 From: Taniya Das Subject: [PATCH v3 00/11] Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform Date: Fri, 8 Nov 2024 09:39:17 +0530 Message-ID: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAO6OLWcC/33OQQ6CMBAF0KuQrq1pEYu48h7GRR0GmQittNhoC He3oMa4Yfl/Mu/PwDw6Qs/2ycAcBvJkTQybVcKg1uaCnMqYWSrSTAqpeAdeyS1vWw6NhStY0zv bNOg4VFWhUedaCMXi/c1hRY/ZPp5irsn31j3nqSCn9qsWC2qQXPAMqnOhyjyPA4fuTkAG1mBbN rkh/VkRW7LSaJVSZ7tc6Exj+W+N76cdxtZT//l8HF/qaQ4uJQEAAA== X-Change-ID: 20241016-qcs615-mm-clockcontroller-cff9aea7a006 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Dmitry Baryshkov , Gabor Juhos , Krzysztof Kozlowski , Bryan O'Donoghue X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XkFmLv-7ZCJ_dxIMkn5bv04_h9ehDhEi X-Proofpoint-ORIG-GUID: XkFmLv-7ZCJ_dxIMkn5bv04_h9ehDhEi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411080034 Add support for multimedia clock controllers on Qualcomm QCS615 platform. Update the defconfig to enable these clock controllers. Global clock controller support https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com/ Signed-off-by: Taniya Das --- Changes in v3: - update PLL configs to use BIT and GENMASK for vco_val and vco_mask for all CCs [Bryan O'Donoghue] - Link to v2: https://lore.kernel.org/r/20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com Changes in v2: - cleanups in clk_alpha_pll_slew_update and clk_alpha_pll_slew_enable functions [Christophe] - update PLL configs for "vco_val = 0x0" shift(20) [Bryan O'Donoghue] - update PLL configs to use lower case for L value [Dmitry] - Link parents for IFE/IPE/BPS GDSCs as Titan Top GDSC [Bryan O'Donoghue, Dmitry] - Remove DT_BI_TCXO_AO from camcc-qcs615 [Dmitry] - Remove HW_CTRL_TRIGGER from camcc-qcs615 [Bryan O'Donoghue] - Update platform name for default configuration [Dmitry] - Link to v1: https://lore.kernel.org/r/20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com --- Taniya Das (11): clk: qcom: Update the support for alpha mode configuration clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Display clock controller clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Video clock controller clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver arm64: defconfig: Enable QCS615 clock controllers .../bindings/clock/qcom,qcs615-camcc.yaml | 60 + .../bindings/clock/qcom,qcs615-dispcc.yaml | 73 + .../bindings/clock/qcom,qcs615-gpucc.yaml | 66 + .../bindings/clock/qcom,qcs615-videocc.yaml | 64 + arch/arm64/configs/defconfig | 4 + drivers/clk/qcom/Kconfig | 35 + drivers/clk/qcom/Makefile | 4 + drivers/clk/qcom/camcc-qcs615.c | 1591 ++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 172 +++ drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/dispcc-qcs615.c | 786 ++++++++++ drivers/clk/qcom/gpucc-qcs615.c | 525 +++++++ drivers/clk/qcom/videocc-qcs615.c | 332 ++++ include/dt-bindings/clock/qcom,qcs615-camcc.h | 110 ++ include/dt-bindings/clock/qcom,qcs615-dispcc.h | 52 + include/dt-bindings/clock/qcom,qcs615-gpucc.h | 39 + include/dt-bindings/clock/qcom,qcs615-videocc.h | 30 + 17 files changed, 3944 insertions(+) --- base-commit: 15e7d45e786a62a211dd0098fee7c57f84f8c681 change-id: 20241016-qcs615-mm-clockcontroller-cff9aea7a006 Best regards,