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[v3,0/2] clk: renesas: rzv2h-cpg: Add CRU and CSI clocks

Message ID 20241202203916.48668-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
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Series clk: renesas: rzv2h-cpg: Add CRU and CSI clocks | expand

Message

Lad, Prabhakar Dec. 2, 2024, 8:39 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to add CRU/CSI clock and reset entries to the
RZ/V2H(P) clock driver.

1] patch#1:
 Allows exclusion of external and specific RZ/V2H(P) clocks, such as those
 in CRU block, from Runtime PM using a new no_pm flag and helper function.
2] patch#2
  Extends the r9a09g057 driver to include PLLVDO, its related CRU clocks
  (CRU0-CRU3), and corresponding reset entries.

v2->v3
-> Replaced `rzv2h-cpg` to `rzv2h` in commit header
-> Switched to use for loop while looping
-> Considering core clocks to be non pm clocks

v1->v2
- Update code to skip external clocks from runtime PM

Cheers,
Prabhakar

Lad Prabhakar (2):
  clk: renesas: rzv2h: Add selective Runtime PM support for clocks
  clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and
    resets

 drivers/clk/renesas/r9a09g057-cpg.c | 45 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.c     | 44 +++++++++++++++++++++++++---
 drivers/clk/renesas/rzv2h-cpg.h     | 18 ++++++++++--
 3 files changed, 100 insertions(+), 7 deletions(-)